Dual-column-parallel CCD sensor and inspection systems using a sensor

• US 10,764,527 B2
• Filed: 04/29/2019
• Issued: 09/01/2020
• Est. Priority Date: 04/06/2016
• Status: Active Grant

• Current Assignee: KLA-Tencor Corporation
• Original Assignee: KLA-Tencor Corporation
• Inventors: Chuang, Yung-Ho Alex, Zhang, Jingjing, Zamek, Sharon, Fielden, John, Contarato, Devis, Brown, David L.
• Primary Examiner(s): Hilaire, Clifford
• Application Number:
  US16/397,072
• Publication Number:
  US 20190253652A1
• Time in Patent Office: 491 Days
• Field of Search: None
• CPC Class Codes: G01N 21/9501 Semiconductor wafers manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G01N 21/956 Inspecting patterns on the surface of objects contactless testing of electronic circuits G01R31/308; testing currency G07D; manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/0008 checking presence/absence
• CPC Class Codes: H01L 27/14812 Special geometry or disposition of pixel-elements, address lines or gate-electrodes
• CPC Class Codes: H01L 27/14825 Linear CCD imagers
• CPC Class Codes: H01L 29/76816 Output structures
• CPC Class Codes: H04N 25/63 applied to dark current
• CPC Class Codes: H04N 25/71 Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
• CPC Class Codes: H04N 25/713 Transfer or readout registers; Split readout registers or multiple readout registers
• CPC Class Codes: H04N 25/715 using frame interline transfer [FIT]
• CPC Class Codes: H04N 25/72 using frame transfer [FT]
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array

Abstract

A dual-column-parallel image CCD sensor utilizes a dual-column-parallel readout circuit including two pairs of cross-connected transfer gates to alternately transfer pixel data (charges) from a pair of adjacent pixel columns to a shared output circuit at high speed with low noise. Charges transferred along the two adjacent pixel columns at a line clock rate are alternately passed by the transfer gates to a summing gate that is operated at twice the line clock rate to pass the image charges to the shared output circuit. A symmetrical Y-shaped diffusion is utilized in one embodiment to merge the image charges from the two pixel columns. A method of driving the dual-column-parallel CCD sensor with line clock synchronization is also described. A method of inspecting a sample using the dual-column-parallel CCD sensor is also described.

Claims

1. An image sensor including:

first and second pixels respectively configured to generate first and second image charges according to one or more pixel control signals; and

a readout circuit comprising;

first and second transfer gates configured to receive the first and second image charges from the first and second pixels, respectively;

third and fourth transfer gates configured to receive the first and second image charges from the first and second transfer gates, respectively;

a summing gate coupled to the third and fourth transfer gates; and

an output circuit coupled to the summing gate,

wherein the first and fourth transfer gates are coupled and the second and third transfer gates are coupled such that a first transfer gate control signal applied to the first transfer gate is substantially simultaneously applied to the fourth transfer gate, and such that a second transfer gate control signal applied to the second transfer gate is substantially simultaneously applied to the third transfer gate, and

wherein the summing gate is configured to receive the first image charge from the third transfer gate during a first time period and to subsequently transfer the first image charge to the output circuit in accordance with a summing gate control signal, and the summing gate is further configured to receive the second image charge from the fourth transfer gate during ad second time period and to subsequently transfer the second image charge to the output circuit in accordance with the summing gate control signal.

2. The sensor of claim 1, wherein the output circuit comprises a floating diffusion configured to receive and store said first and second image charges, and an amplifier coupled to the floating diffusion and configured to generate a first output voltage signal when the first image charge is stored on the floating diffusion, and to generate a second output voltage signal when the second image charge is stored on the floating diffusion.

3. The sensor of claim 1, further comprising an array of pixels arranged in an even number of columns,

wherein the readout circuit includes a plurality of readout structures, each said readout structure connected to an associated pair of said columns and including four transfer gates, a summing gate, and an amplifier.

4. The sensor of claim 3, wherein said amplifier of each said readout structure comprises a metal interconnect, wherein capacitances of the metal interconnects of different amplifiers are substantially similar.

5. The sensor of claim 3, wherein each said amplifier comprises a metal interconnect, wherein areas of the metal interconnects of different amplifiers are substantially similar.

6. The sensor of claim 3, wherein the array of pixels consists of one or more rows of pixels.

7. An image sensor comprising:

a semiconductor substrate;

a Y-shaped buried diffusion formed in the substrate and including parallel first and second elongated portions connected to a third elongated portion by way of a V-shaped merge section;

a plurality of pixel gate structures respectively formed over the first and second elongated portions;

first and second transfer gate structures respectively formed over the first and second elongated portions and disposed between the pixel gate structures and the V-shaped merge section;

third and fourth transfer gate structures respectively formed over the first and second elongated portions and respectively disposed between the first and second transfer gate structures and the V-shaped merge section;

a summing gate structure formed over the V-shaped merge section; and

an output circuit coupled to the third elongated portion,

wherein the first and fourth transfer gate structures are coupled such that a first control signal applied to the first transfer gate structure is substantially simultaneously applied to the fourth transfer gate structure, and

wherein the second and third transfer gate structures are coupled such that a second control signal applied to the second transfer gate structure is substantially simultaneously applied to the third transfer gate structure.

8. The image sensor of claim 7, wherein the first and fourth transfer gate structures are connected by a first conductive linking structure such that said first control signal applied to the first transfer gate structure is transmitted by said first conductive linking structure to said fourth transfer gate structure.

9. The image sensor of claim 8, wherein the first conductive linking structure comprises one of metal and polycrystalline silicon.

10. The image sensor of claim 8, wherein the first transfer gate structure, the fourth transfer gate structure, and the first conductive linking structure comprise an integral composite polycrystalline silicon structure.

11. The image sensor of claim 7, wherein the summing gate summing gate structure is configured to receive a first image charge from the first elongated portion during a first time period and to subsequently transfer the first image charge to the third elongated portion in accordance with a summing gate control signal, and the summing gate is further configured to receive a second image charge from the second elongated portion during a second time period and to subsequently transfer the second image charge to the third elongated portion in accordance with a summing gate control signal.

12. The image sensor of claim 7, wherein the summing gate summing gate structure comprises a tapered polycrystalline silicon structure having an upstream edge facing the first and second elongated portions and a downstream edge facing the third elongated portion, and wherein a length of the upstream edge is greater than a length of the downstream edge.

13. The image sensor of claim 7, further comprising a tapered output gate structure disposed between the summing gate structure and the third elongated portion.

14. The image sensor of claim 7, wherein the output circuit comprises:

a floating diffusion formed in the third elongated portion; and

an amplifier disposed on the substrate and operably coupled to the floating diffusion by a conductive structure.

15. The image sensor of claim 14,

wherein the amplifier comprises a first-stage gain transistor, and

wherein the conductive structure comprises a polycrystalline silicon structure including a lower poly portion extending through a contact hole to the floating diffusion, and a horizontal poly portion extending from the lower poly portion, wherein a portion of said horizontal poly portion forms a gate structure for the first-stage gain transistor.