Autonomous memory architecture

• US 10,769,097 B2
• Filed: 10/02/2017
• Issued: 09/08/2020
• Est. Priority Date: 09/11/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Eilert, Sean, Leinwander, Mark, Hulbert, Jared
• Primary Examiner(s): Chbouki, Tarek
• Application Number:
  US15/722,624
• Publication Number:
  US 20180024966A1
• Time in Patent Office: 1,072 Days
• CPC Class Codes: G06F 15/17318 Parallel communications techniques, e.g. gather, scatter, reduce, roadcast, multicast, all to all

Abstract

An autonomous memory device in a distributed memory sub-system can receive a database downloaded from a host controller. The autonomous memory device can pass configuration routing information and initiate instructions to disperse portions of the database to neighboring die using an interface that handles inter-die communication. Information is then extracted from the pool of autonomous memory and passed through a host interface to the host controller.

Claims

1. A system, comprising:

a host interface to couple to a host device; and

a distributed array of autonomous memory devices in communication with the host device, the distributed array of autonomous memory devices being implemented by a plurality of die, each of the autonomous memory devices being formed on a single die of the plurality of die, each single die comprising a microcontroller that is embedded on the single die to perform computations independently of the host device, each of the autonomous memory devices being configured to maintain a routing table to keep track of the other autonomous memory devices in the distributed array and to store a latency cost based on a location of the autonomous memory device in communication with the other autonomous memory devices in the distributed array, the routing table enabling the autonomous memory device to route a message to another autonomous memory device in the distributed array.

2. The system of claim 1, wherein each of the autonomous memory devices includes its own operating system.

3. The system of claim 1, wherein the host device is configured to assign a unique static address to each of the autonomous memory devices.

4. The system of claim 1, wherein the host device is configured to dynamically determine an address of each of the autonomous memory devices during an operation of respective ones of the autonomous memory devices.

5. The system of claim 1, wherein each of the autonomous memory devices is to build the routing table using a scan technique to keep track of remaining ones of the autonomous memory devices within the distributed array.

6. The system of claim 1, wherein each of the autonomous memory devices is configured to store a latency cost based on a location of the autonomous memory devices in communication with another one of the autonomous memory devices.

7. The system of claim 1, wherein each of the autonomous memory devices is configured to execute a search and destroy algorithm simultaneously with others of the autonomous memory devices to isolate and disable an occurrence of a target virus.

8. A memory system, comprising:

a distributed array of autonomous memory devices in communication with a host, the distributed array of autonomous memory devices being implemented by a plurality of die, each of the autonomous memory devices being formed on a single die of the plurality of die, each single die comprising a microcontroller that is embedded on the single die and that is configured to perform computations on a database, each of the autonomous memory devices having a first interface to communicate with the host and at least one second interface to communicate with others of the autonomous memory devices in the distributed array, each of the autonomous memory devices being configured to maintain a routing table to keep track of the other autonomous memory devices in the distributed array and to store a latency cost based on a location of the autonomous memory device in communication with the other autonomous memory devices in the distributed array, the routing table enabling the autonomous memory device to route a message to another autonomous memory device in the distributed array.

9. The memory system of claim 8, further comprising a memory within each of the autonomous memory devices to store information about how the database is organized.

10. The memory system of claim 8, wherein the at least one second interface is configured to transfer messages that contain a command and a list of parameters to others of the autonomous memory devices.

11. The memory system of claim 10, wherein the messages include a transfer of data, address information that refers to data in the distributed array, and object identifiers that reference an object located in the distributed array.

12. A system, comprising:

a distributed array of autonomous memory devices, each of the autonomous memory devices having a host interface to communicate with a host controller, being formed on a single die that comprises a microcontroller embedded on the single die, being configured to perform computations on a database, and being configured to maintain a routing table to keep track of the other autonomous memory devices in the distributed array and to store a latency cost based on a location of the autonomous memory device in communication with the other autonomous memory devices in the distributed array, the routing table enabling the autonomous memory device to route a message to another autonomous memory device in the distributed array; and

a memory in the autonomous memory devices, at least one of the autonomous memory devices to receive the database through the host interface from the host controller and to store the database in the memory of the at least one autonomous memory device, the microcontroller within the at least one of the autonomous memory devices to disperse portions of the database to a neighboring autonomous memory device in the distributed array through inter-die communication ports in each of the autonomous memory devices.

13. The system of claim 12, wherein the memory in at least one of the autonomous memory devices is to receive software from the host controller to allow the at least one autonomous memory device to control other ones of the autonomous memory devices.

14. The system of claim 12, wherein each of the autonomous memory devices is configured to parse and execute operations autonomously within selected ones of the autonomous memory devices.

15. The system of claim 14, wherein the selected ones of the autonomous memory devices are further configured to accumulate and report results from the executed operations to the host controller when the operations are complete.

16. The system of claim 12, wherein selected ones of the autonomous memory devices are configured to execute stored routines, provided by libraries and stored within respective ones of the memories, to build applications.

17. The system of claim 12, further comprising acceleration hardware within each of the autonomous memory devices.

18. The system of claim 12, wherein each of the autonomous memory devices has multiple inter-die communication ports to communicate simultaneously with each of multiple nearest-neighbor ones of remaining ones of the autonomous memory devices.

19. The system of claim 12, wherein each of the autonomous memory devices has at least one autonomous memory management mechanism selected from mechanisms including a wear leveling mechanism, an error detection and correction mechanism, and a compression and decompression mechanism.