Dual threshold voltage devices having a first transistor and a second transistor

• US 10,770,510 B2
• Filed: 01/08/2018
• Issued: 09/08/2020
• Est. Priority Date: 01/08/2018
• Status: Active Grant

• Current Assignee: Integrated Silicon Solution Incorporated (Uphill Investment Co.)
• Original Assignee: Spin Memory, Inc.
• Inventors: Sharma, Gian, Levi, Amitay, Kim, Kuk-Hwan
• Primary Examiner(s): Nguyen, Khiem D
• Application Number:
  US15/865,135
• Publication Number:
  US 20190214431A1
• Time in Patent Office: 974 Days
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/80 Constructional details

Abstract

A device having two transistors with dual thresholds, and a method of fabricating the device, including fabricating a silicide source, a conductive layer, and contacts to a plurality of layers of the device, is provided. The device has a core and a plurality of layers that surround the core in succession, including a first layer, a second layer, a third layer, and a fourth layer. The device further comprises a first input terminal coupled to the core, the first input terminal being configured to receive a first voltage and a second input terminal coupled to the fourth layer, the second input terminal being configured to receive a second voltage. The device comprises a common source terminal coupled to the core and the fourth layer. A memory device, such as an MTJ, may be coupled to the device.

Claims

1. A device comprising:

a core;

a plurality of layers that surround the core in succession, including a first layer, a second layer, a third layer, and a fourth layer, wherein;

the core, the first layer, and the second layer correspond to a first transistor;

the second layer, the third layer, and the fourth layer correspond to a second transistor; and

the second layer is a common channel;

a first input terminal coupled to the core, the first input terminal being configured to receive a first voltage;

a second input terminal coupled to the fourth layer, the second input terminal being configured to receive a second voltage;

a common source terminal coupled to the core and the fourth layer; and

a cylindrical source contact coupled to the common source terminal.

2. The device of claim 1, wherein:

the common channel comprises a channel source and a channel drain; and

the device further comprises a magnetic tunnel junction (MTJ) coupled to the channel drain.

3. The device of claim 2, wherein:

the MTJ includes a storage layer, a spacer layer, and a reference layer; and

the reference layer of the MTJ is coupled to the channel drain.

4. The device of claim 1, wherein:

the core is vertical and cylindrical in shape;

the plurality of layers annularly surrounds the vertical cylindrical core; and

the core surrounded by the plurality of layers creates a cylindrical pillar.

5. The device of claim 4, wherein:

the first transistor is configured to have a first threshold voltage having a first magnitude;

the second transistor is configured to have a second threshold voltage having a second magnitude; and

the second magnitude is distinct from the first magnitude.

6. The device of claim 5, wherein:

the first voltage is based on one or more of;

dopant type of the channel, dopant level of the channel, dielectric constant of a first dielectric layer, thickness of the first dielectric layer and work function of the core; and

the second voltage is based on channel dopant type, channel dopant level, thickness of a third dielectric layer and work function of a fourth conductive layer.

7. The device of claim 5, wherein a magnitude each of the threshold voltages and/or the applied voltages effect one another.

8. The device of claim 5, wherein the first threshold voltage and the second threshold voltage are selected by changing one or more properties of the device selected from the group consisting of:

a dopant of the device, a thickness of one or more of the plurality of layers, and material compositions of the first transistor and the second transistor.

9. The device of claim 1, wherein the common source terminal is composed of silicided areas coupled to a bottom plane of the second layer.

10. The device of claim 1, wherein:

the core is composed of a conductive material;

the first layer is a first dielectric layer that surrounds the core;

the second layer surrounds the first dielectric layer;

the third layer is a third dielectric layer that surrounds the second layer; and

the fourth layer is composed of a conductive material and surrounds the third dielectric layer.

11. The device of claim 1, wherein the fourth layer is composed of a polycide.