Isolation structure, semiconductor device having the same, and method for fabricating the isolation structure

• US 10,770,542 B2
• Filed: 06/30/2015
• Issued: 09/08/2020
• Est. Priority Date: 09/26/2011
• Status: Active Grant

• Current Assignee: SK Keyfoundry Incorporated
• Original Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Inventors: Choi, Hyung-suk, Jung, Hyun-tae, Park, Eungryul, Lee, Da-soon
• Primary Examiner(s): Carpenter, Robert K
• Application Number:
  US14/788,090
• Publication Number:
  US 20150303253A1
• Time in Patent Office: 1,897 Days
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps

Abstract

An isolation structure of a semiconductor, a semiconductor device having the same, and a method for fabricating the isolation structure are provided. An isolation structure of a semiconductor device may include a trench formed in a substrate, an oxide layer formed on a bottom surface and an inner sidewall of the trench, a filler formed on the oxide layer to fill a part of inside of the trench, and a fourth oxide layer filling an upper portion of the filler of the trench to a height above an upper surface of the trench, an undercut structure being formed on a boundary area between the inner sidewall and the oxide layer.

Claims

1. A semiconductor device, comprising:

a substrate having a top surface;

an isolation structure comprising;

a trench formed in the substrate;

an oxide layer formed on a sidewall of the trench;

a filler formed on the oxide layer to fill a part of inside of the trench; and

an additional oxide layer filling an upper portion of the trench,

a buried layer formed to abut the trench and having a depth shallower than a depth of the trench;

a first well region and a second well region formed on the buried layer, the first well region abutting against the second well region and the first well region having a depth equal to a depth of the second well region;

a third well region formed in the first well region and having a same conductivity type as the first well region;

a drain region formed in the second well region;

a source region formed in the third well region;

a gate insulating layer formed on the first well region and the second well region; and

a gate electrode formed on the gate insulating layer.

2. The semiconductor device of claim 1, wherein the filler comprises a polysilicon material.

3. The semiconductor device of claim 2, wherein the oxide layer and the additional oxide layer fully enclose the polysilicon material.

4. The semiconductor device of claim 1, wherein a top surface of the filler is lower than a top surface of the trench.

5. The semiconductor device of claim 1, further comprising a field oxide layer formed on one side or both sides of the trench by LOCOS.

6. The semiconductor device of claim 1, wherein the oxide layer comprises:

a first oxide layer formed on the sidewall of the trench; and

a second oxide layer formed on the first oxide layer, wherein the first oxide layer and the second oxide layer have a same material with each other.

7. The semiconductor device of claim 6, wherein an uppermost surface of the first oxide layer is approximately coplanar with an uppermost surface of the second oxide layer.

8. The semiconductor device of claim 6, wherein each of the first oxide layer and the second oxide layer has a thickness ranging between 2500 and 5000 Å

.

9. The semiconductor device of claim 6, further comprising:

a nitride layer formed on the first oxide layer, such that the nitride layer is positioned between the first oxide layer and the second oxide layer.

10. The semiconductor device of claim 1, wherein a portion of the sidewall of the trench protrudes inwards to form an undercut structure.

11. The semiconductor device of claim 10, wherein the trench is formed at a depth of 10 to 40 μ

m from the top surface of the substrate, and the undercut structure is formed at a depth of 3 to 7 μ

m from the top surface of the substrate.

12. The semiconductor device of claim 1, wherein the oxide layer is in direct contact with the buried layer and the first well region.

13. A semiconductor device, comprising:

an isolation structure comprising;

at least one trench formed in a substrate;

a composite layer comprising an oxide layer and a nitride layer formed on a sidewall of the trench;

a filler formed on the composite layer; and

an additional oxide layer formed on the filler,

a buried layer formed in the substrate and disposed to abut the trench having a depth larger than a depth of the buried layer;

a first well region and a second well region formed on the buried layer, the first well region abutting against the second well region and having a depth equal to a depth of the second well region;

a source region formed in the first well region;

a drain region formed in the second well region;

a gate insulating layer formed on the first well region and the second well region; and

a gate electrode formed on the gate insulating layer,

wherein the isolation structure is in direct contact with the first well region and the second well region.

14. The semiconductor device of claim 13, further comprising:

a third well region formed in the first well region and having a same conductivity type as the first well region,

wherein the third well region encloses the source region and overlaps with the gate electrode.

15. The semiconductor device of claim 13, further comprising:

a first field oxide layer and a second field oxide layer formed on both sides of the trench; and

a third field oxide layer formed on the second well region and overlapping with the gate electrode,

wherein the drain region is formed between the second field oxide layer and the third field oxide layer.

16. The semiconductor device of claim 13, wherein the filler comprises a polysilicon material.

17. The semiconductor device of claim 13, wherein the trench comprises a tapered deep trench structure that gradually narrows towards the substrate.

18. A semiconductor device, comprising:

a substrate having a top surface;

a first well region of a first conductivity type formed in the substrate;

a second well region of a second conductivity type abutting against the first well region;

a source region formed in the first well region;

a drain region formed in the second well region;

an isolation structure to enclose the first well region and the second well region, the isolation structure comprising;

at least one trench formed in the substrate;

a polysilicon layer filled in the at least one trench; and

an oxide layer fully enclosing the polysilicon layer;

a field oxide layer formed on one side or both sides of the at least one trench,

a buried layer formed to abut the at least one trench and having a depth smaller than a depth of the trench;

a gate insulating layer formed on the first well region and the second well region; and

a gate electrode formed on the gate insulating layer.

19. The semiconductor device of claim 18, further comprising:

a third well region formed in the first well region and having a same conductivity type as the first well region,

wherein the third well region encloses the source region and overlaps with the gate electrode.

20. The semiconductor device of claim 19, wherein the third well region has a depth larger than a depth of the field oxide layer, and having a depth smaller than a depth of the second well region.