Methods of fabricating dual threshold voltage devices

• US 10,770,561 B2
• Filed: 01/29/2019
• Issued: 09/08/2020
• Est. Priority Date: 01/08/2018
• Status: Active Grant

• Current Assignee: Integrated Silicon Solution Incorporated (Uphill Investment Co.)
• Original Assignee: Spin Memory, Inc.
• Inventors: Sharma, Gian, Levi, Amitay, Kim, Kuk-Hwan
• Primary Examiner(s): Smith, Zandra V
• Assistant Examiner(s): Joy, Jeremy J
• Application Number:
  US16/261,414
• Publication Number:
  US 20190311956A1
• Time in Patent Office: 588 Days
• CPC Class Codes: H01L 21/32053 of metal-silicide layers
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/4011 for data storage electrodes
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices

Abstract

An annular device is provided. The annular device includes a first transistor including a first input terminal and a second transistor including a second input terminal. The first input terminal and the second input terminal extend radially outward from the annular device, and wherein the first input terminal is aligned with the second input terminal.

Claims

1. An annular device, comprising:

a cylindrical pillar, comprising;

a vertical cylindrical core; and

a plurality of layers that surround the vertical cylindrical core in succession, the plurality of layers including a first layer, a second layer, a third layer, and a fourth layer,

wherein;

the core, the first layer, and the second layer correspond to a first transistor including a first input terminal, wherein the first transistor is configured to have a first threshold voltage having a first magnitude; and

the second layer, the third layer, and the fourth layer correspond to a second transistor including a second input terminal, wherein the second transistor is configured to have a second threshold voltage having a second magnitude distinct from the first magnitude.

2. The annular device of claim 1, wherein:

the second layer is a common channel having a channel source and a channel drain;

the first input terminal is coupled to the core, the first input terminal being configured to receive a first voltage for the first transistor; and

the second input terminal is coupled to the fourth layer, the second input terminal being configured to receive a second voltage for the second transistor.

3. The annular device of claim 2, further comprising a magnetic tunnel junction (MTJ) coupled to the channel drain.

4. The annular device of claim 2, further comprising a cylindrical source contact coupled to the channel source.

5. The annular device of claim 3, wherein:

the MTJ includes a storage layer, a spacer layer, and a reference layer; and

the reference layer of the MTJ is coupled to the channel drain.

6. The annular device of claim 1, wherein:

the first layer is a first dielectric layer;

the third layer is a third dielectric layer; and

the first threshold voltage and the second threshold voltage are based on respective thicknesses for the first dielectric layer and the third dielectric layer.

7. The annular device of claim 1, wherein the first threshold voltage and the second threshold voltage are selected by changing one or more properties of the annular device selected from the group consisting of:

a dopant of the annular device, a material composition of the first input terminal, a work function of the first input terminal, a material composition of the second input terminal, and a work function of the second input terminal.

8. The annular device of claim 1, wherein:

the core is conductive;

the first layer is a first dielectric layer that surrounds the core;

the second layer surrounds the first dielectric layer and is composed of a semiconductor material;

the third layer is a third dielectric layer that surrounds the second layer; and

the fourth layer is conductive and surrounds the third dielectric layer.

9. The annular device of claim 1, wherein the fourth layer is composed of a polycide.

10. The annular device of claim 1, wherein the core is composed of a Tantalum material.

11. The annular device of claim 1, wherein the second layer has a height that is distinct from a height of the core.

12. The annular device of claim 1, wherein the second layer has a height that is distinct from a respective height of the third layer and the fourth layer.

13. The annular device of claim 1, wherein the first input terminal and the second input terminal extend radially outward from the annular device.

14. The annular device of claim 1, wherein the first input terminal is aligned with the second input terminal.

15. An annular device, comprising:

a core; and

a plurality of layers that surround the core in succession, the plurality of layers including a first layer, a second layer, a third layer, and a fourth layer, wherein;

the core, the first layer, and the second layer correspond to a first transistor including having a first input terminal; and

the second layer, the third layer, and the fourth layer correspond to a second transistor including having a second input terminal; and

the second layer is a common channel having a channel source and a channel drain;

the first input terminal is coupled to the core, the first input terminal being configured to receive a first voltage for the first transistor; and

the second input terminal is coupled to the fourth layer, the second input terminal being configured to receive a second voltage for the second transistor.