Semiconductor device

• US 10,777,549 B2
• Filed: 06/21/2019
• Issued: 09/15/2020
• Est. Priority Date: 07/18/2017
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Shirakawa, Tohru
• Primary Examiner(s): Mandala, Victor A
• Application Number:
  US16/448,522
• Publication Number:
  US 20190312029A1
• Time in Patent Office: 452 Days
• CPC Class Codes: H01L 21/8234 MIS technology , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/06 including a plurality of individual components in a non-repetitive configuration
• CPC Class Codes: H01L 27/0716 in combination with vertical bipolar transistors and diodes, or capacitors, or resistors
• CPC Class Codes: H01L 27/0727 in combination with diodes, or capacitors or resistors
• CPC Class Codes: H01L 29/06 characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
• CPC Class Codes: H01L 29/0611 for increasing or controlling the breakdown voltage of reverse biased devices H01L29/0661 takes precedence
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/417 carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/739 controlled by field-effect, e.g. bipolar static induction transistors [BSIT] unijunction transistors H01L29/705
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes
• CPC Class Codes: H01L 29/8613 Mesa PN junction diodes

Abstract

An IGBT region in which an IGBT is disposed and a FWD region in which a FWD connected in antiparallel to the IGBT is disposed are provided in an active region of a semiconductor chip. In the active region, the FWD region is provided in plural separated from each other. The IGBT region is a continuous region between the FWD regions. In the IGBT region and the FWD region, first and second gate trenches are disposed in striped-shape layouts that are parallel to a front surface of the semiconductor chip and extend along a same first direction. The second gate trenches of the FWDs of the FWD regions are disposed separated from the first gate trenches of the IGBT in the IGBT region. This structure enables degradation of element characteristics to be prevented, and heat dissipation of the semiconductor chip and the degrees of freedom in design to be enhanced.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate; and

an active region through which current flows, provided on the semiconductor substrate, the active region including a first element region and a plurality of second element regions, wherein

the first element region includes a first element having a first trench gate structure, the first trench gate structure including

a first trench provided on a first main surface side of the semiconductor substrate, and

a first gate electrode provided in the first trench via a first gate insulating film,

the plurality of second element regions each include a second element having a second trench gate structure, the second trench gate structure including

a second trench provided on the first main surface side of the semiconductor substrate, separated from the first trench, and

a second gate electrode provided in the second trench via a second gate insulating film,

the second element regions being spaced apart from each other, the first element region being a single continuous region and being disposed in a part of the active region, the part of the active region being free of the second element regions,

the active region has a rectangular outer periphery including a first side extending in a first direction and a second side opposite to the first side,

each second element region is disposed in a striped-shape layout that is parallel to a first main surface of the semiconductor substrate, and

the plurality of second element regions include a plurality of first second-element-regions and a plurality of second second-element-regions,

the first second-element-regions extending from the first side toward the second side in the first direction,

the second second-element-regions extending from the second side toward the first side in the first direction,

each of the first second-element-regions being disposed at a position different from each of the second second-element-regions along a second direction orthogonal to the first direction, and

a total number of the first second-element-regions and a total number of the second second-element-regions are the same.

2. The semiconductor device according to claim 1, wherein each second element region is disposed near an outer periphery of the active region.

3. The semiconductor device according to claim 1, wherein a first length of said each second element region along the first direction is longer than a second length of said each second element region along the second direction.

4. The semiconductor device according to claim 1, wherein a distance between adjacent two second element regions in the second direction is equal to or greater than the second length of said each second element region along the second direction.

5. The semiconductor device according to claim 1, wherein the second length of said each second element region along the second direction is at least 50 μ

m.

6. The semiconductor device according to claim 1, wherein

the first element further includes:

a first semiconductor region of a first conductivity type provided on the semiconductor substrate;

a second semiconductor region of a second conductivity type provided in a surface layer at the first main surface of the semiconductor substrate, the second semiconductor region being in contact with the first semiconductor region;

a third semiconductor region of the first conductivity type selectively provided in the second semiconductor region;

a fourth semiconductor region of the second conductivity type provided in a surface layer at a second main surface of the semiconductor substrate, the fourth semiconductor region being in contact with the first semiconductor region;

a first electrode in contact with the second semiconductor region and the third semiconductor region; and

a second electrode in contact with the fourth semiconductor region, and

the first trench penetrates the third semiconductor region and the second semiconductor region, and reaches the first semiconductor region,

the second element further includes;

the first semiconductor region and the second semiconductor region extending from the first element region to said each second element region;

a fifth semiconductor region of the first conductivity type provided in the surface layer at the second main surface of the semiconductor substrate,

the fifth semiconductor region being in contact with the first semiconductor region and

the fourth semiconductor region;

the first electrode in contact with the second semiconductor region; and

the second electrode in contact with the fifth semiconductor region, and

the second trench penetrates the second semiconductor region and reaches the first semiconductor region, and

the second gate electrode is in contact with the fifth semiconductor region.

7. The semiconductor device according to claim 1, wherein

the first trench includes a plurality of first trenches each having two ends, each first trench extending in a direction parallel to the first main surface of the semiconductor substrate and being disposed in a striped-shape layout extending in the first direction,

the second trench includes a plurality of second trenches each having two ends, each second trench extending in a direction parallel to the first main surface of the semiconductor substrate and being disposed in a striped-shape layout extending in the first direction,

one of the two ends of one of the first trenches facing one of the two ends of a corresponding one of the second trenches along the first direction, and

the semiconductor device further comprising a sixth semiconductor region of the second conductivity type provided between and contacting the one of the two end of the one of the first trenches and the one of the two ends of the corresponding one of the second trenches.

8. The semiconductor device according to claim 6, wherein

the first trench includes a plurality of first trenches each having two ends, each first trench extending in a direction parallel to the first main surface of the semiconductor substrate and being disposed in a striped-shape layout extending in the first direction,

the second trench includes a plurality of second trenches each having two ends, each second trench extending in a direction parallel to the first main surface of the semiconductor substrate and being disposed in a striped-shape layout extending in the first direction,

one of the two ends of one of the first trenches facing one of the two ends of a corresponding one of the second trenches along the first direction, and

the semiconductor device further comprising a sixth semiconductor region of the second conductivity type provided between and contacting the one of the two end of the one of the first trenches and the one of the two ends of the corresponding one of the second trenches.

9. The semiconductor device according to claim 7, wherein a depth of the sixth semiconductor region is greater than a depth of the first trench and a depth of the second trench.

10. The semiconductor device according to claim 6, further comprising

a boundary region between the first element region and one of the second element regions, wherein

the boundary region includes the first semiconductor region having a surface layer in which the second semiconductor region is disposed.

11. The semiconductor device according to claim 10, wherein the second semiconductor region in the boundary region further includes

a seventh semiconductor region of the second conductivity type disposed in the surface layer of the second semiconductor region, the seventh semiconductor region having an impurity concentration higher than an impurity concentration of the second semiconductor region;

and

an eighth semiconductor region of the first conductivity type disposed at a bottom surface of the second semiconductor region, the eighth semiconductor region having an impurity concentration higher than an impurity concentration of the first semiconductor region.

12. The semiconductor device according to claim 11, wherein the seventh semiconductor region is electrically connected to the second gate electrode.

13. The semiconductor device according to claim 8, further comprising

a boundary region between the first element region and one of the second element regions, wherein

the boundary region further includes

the sixth semiconductor region, the six semiconductor region being provided in the surface layer of the first semiconductor region and covering bottoms of the first trench and a corresponding one of the second trenches, and

a ninth semiconductor region of the second conductivity type provided in a surface layer of the sixth semiconductor region, the ninth semiconductor region having an impurity concentration higher than an impurity concentration of the sixth semiconductor region.

14. The semiconductor device according to claim 13, wherein the ninth semiconductor region is electrically connected to the second gate electrode.

15. The semiconductor device according to claim 1, further comprising

an edge termination region provided between the active region and an edge of the semiconductor substrate in plan view of the semiconductor device, the edge termination region surrounding a periphery of the active region, wherein

the active region has a rectangular outer periphery including a first pair of opposing sides in a first direction and a second pair of opposing sides in a second direction orthogonal to the first direction,

each second element region is disposed in a striped-shape layout that is parallel to a first main surface of the semiconductor substrate, and extends from one of the first pairs of opposing sides toward the other one of the first pair of opposing sides along the second direction, and

the outer periphery of the active region is a boundary between the active region and the edge termination region.

16. The semiconductor device according to claim 6, further comprising:

an edge termination region provided between the active region and an edge of the semiconductor substrate in plan view of the semiconductor device, the edge termination region surrounding a periphery of the active region, wherein

the active region has a rectangular outer periphery including a first pair of opposing sides in a first direction and a second pair of opposing sides in a second direction orthogonal to the first direction,

each second element region is disposed in a striped-shape layout that is parallel to a first main surface of the semiconductor substrate, and extends from one of the first pairs of opposing sides toward the other one of the first pair of opposing sides along the second direction, and

the outer periphery of the active region is a boundary between the active region and the edge termination region.

17. The semiconductor device according to claim 1, wherein

the first element region is an insulated gate bipolar transistor, and

each of the plurality of second element regions is a free wheeling diode.