High accuracy timestamp support

• US 10,778,360 B1
• Filed: 12/06/2018
• Issued: 09/15/2020
• Est. Priority Date: 12/06/2018
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Wang, Lifeng, Li, Jinhua, Hu, Yong
• Primary Examiner(s): Jaroenchonwanit, Bunjob
• Application Number:
  US16/212,391
• Time in Patent Office: 649 Days
• Field of Search: None
• CPC Class Codes: H04J 3/0667 Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays arrangements for monitoring round trip delays in packet switching networks H04L43/0864
• CPC Class Codes: H04J 3/0697 Synchronisation in a packet node
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

Apparatus and associated methods relate to high accuracy timestamp support by controlling a first phase relationship between an outbound signal transmitted by a transmitting circuit and a local reference clock signal, measuring a second phase difference between a received data signal and the local reference signal, and measuring a third phase difference between a received time of day (RXTOD) signal and the local reference signal. In an illustrative example, a state machine circuit may be operated to control the first phase relationship, a phase measuring circuit may be configured to measure the second phase difference and the third phase difference. By comparing results obtained from phase control and phase measurement, the time of day (TOD) of each transmitted/received bit can be calculated at 1-bit level accuracy and achieve 1-bit level accuracy in the timestamp.

Claims

1. An integrated circuit, comprising:

a transmitting circuit configured to transmit an outbound signal to an external interface;

a receiving circuit configured to receive a return signal from the external interface;

a clock generation circuit configured to generate a local reference clock signal to both the transmitting circuit and the receiving circuit;

a state machine circuit coupled to the transmitting circuit to control a phase relationship between the outbound signal and the local reference clock signal; and

,

a phase measuring circuit coupled to the receiving circuit to measure a phase difference between the return signal and the local reference clock signal,

wherein the outbound signal comprises a transmitted data signal, and the return signal comprises a received data signal and a received time of day RXTOD signal.

2. The integrated circuit of claim 1, wherein the state machine circuit is configured to align the phase of the transmitted data signal with the local reference clock signal.

3. The integrated circuit of claim 1, wherein the outbound signal further comprises a transmitted time of day TXTOD signal, and the state machine circuit is configured to control a first phase difference between the transmitted time of day TXTOD signal with the local reference clock signal.

4. The integrated circuit of claim 1, wherein the phase measuring circuit is configured to measure a second phase difference between the received data signal and the local reference clock signal.

5. The integrated circuit of claim 1, wherein the phase measuring circuit is configured to measure a third phase difference between the received time of day RXTOD signal and the local reference clock signal.

6. The integrated circuit of claim 2, wherein the transmitting circuit further comprises a buffer, the buffer status is indicated by an indication bit to find the alignment point.

7. The integrated circuit of claim 1, wherein the transmitting circuit is configured to operate in an oversampling mode.

8. The integrated circuit of claim 1, wherein the receiving circuit is configured to operate in an oversampling mode.

9. The integrated circuit of claim 1, wherein the phase measuring circuit further comprises a mixed-mode clock manager MMCM and a phase measure block, wherein the MMCM is configured to receive the local reference clock signal, and the phase measure block is configured to receive the received data signal and an output of the MMCM.

10. The integrated circuit of claim 9, wherein phase measuring circuit further comprises a plurality of slices of the phase measure block configured to receive a plurality of return signals.

11. A method to support an accurate timestamp, comprising:

generating, with a clock generation circuit, a local reference clock signal to a transmitting circuit and a receiving circuit;

transmitting, with the transmitting circuit, an outbound signal to an external interface;

controlling, with a state machine circuit coupled to the transmitting circuit, a phase relationship between the outbound signal and the local reference clock signal;

receiving, with the receiving circuit, a return signal from the external interface; and

,

measuring, with a phase measuring circuit coupled to the receiving circuit, a phase difference between the return signal and the local reference clock signal,

wherein the outbound signal comprises a transmitted data signal, and the return signal comprises a received data signal and a received time of day RXTOD signal.

12. The method of claim 11, wherein the controlling further comprises aligning the transmitted data signal with the local reference clock signal.

13. The method of claim 12, wherein the aligning further comprises:

presetting a transmitter buffer with a predetermined occupancy rate;

moving the phase of the transmitted data signal until the buffer has an occupancy less than the predetermined occupancy rate;

moving the phase of the transmitted data signal until the buffer has an occupancy just above the predetermined occupancy; and

,

locking the phase of the transmitted data signal.

14. The method of claim 13, wherein the occupancy rate is indicated by an indication bit.

15. The method of claim 13, wherein the predetermined occupancy is 50%.

16. The method of claim 11, wherein the phase measuring circuit further comprises a mixed-mode clock manager MMCM and a phase measure block.

17. The method of claim 16, further comprising:

receiving, with the MMCM, the local reference clock signal and generating an output signal; and

, detecting, with the phase measure block, a phase difference in response to the return signal and the output signal.

18. The method of claim 16, wherein the phase measuring circuit further comprises a plurality of slices of the phase measure blocks configured to measure phase differences between a plurality of return signals with the local reference clock signal.

19. The method of claim 11, wherein the outbound signal further comprises a transmitted time of day TXTOD signal.

20. The method of claim 11, further comprising configuring the transmitting circuit and the receiving circuit to operate in an oversampling mode.