Methods and systems for parsing and executing instructions to retrieve data using autonomous memory

• US 10,778,815 B2
• Filed: 05/25/2018
• Issued: 09/15/2020
• Est. Priority Date: 12/02/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Curewitz, Kenneth M, Eilert, Sean, Akel, Ameen D., Wang, Hongyu
• Primary Examiner(s): Petranek, Jacob
• Application Number:
  US15/989,920
• Publication Number:
  US 20190007529A1
• Time in Patent Office: 844 Days
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers

Abstract

A method, an apparatus, and a system have been disclosed. An embodiment of the method includes an autonomous memory device receiving a set of instructions, the memory device executing the set of instructions, combining the set of instructions with any data recovered from the memory device in response to the set of instructions into a packet, and transmitting the packet from the memory device.

Claims

1. A method performed by a memory device, comprising:

receiving and parsing a set of instructions at a memory processing apparatus, of the memory device, using a packet parser;

executing the set of instructions, using at least one execution unit of the memory processing apparatus, to retrieve data from a storage memory of the memory device;

combining, into a packet using a packet generator of the memory processing apparatus, the set of instructions with the data retrieved from the storage memory; and

communicating the packet from the memory processing apparatus to a memory controller connected to the memory device.

2. The method of claim 1, wherein the receiving of the set of instructions comprises receiving the set of instructions via a network coupled to the memory device, and wherein the communicating of the packet comprises transmitting the packet via the network.

3. The method of claim 1, wherein the parsing of the set of instructions comprises parsing a received packet that includes the set of instructions, by:

loading a program counter with an initial program counter value associated with the received set of instructions;

loading an instruction memory with the set of instructions; and

.

loading a register file with a set of initial conditions associated with the set of instructions.

4. The method of claim 3, wherein executing the set of instructions comprises:

calculating a new program counter value after executing a first instruction of the set of instructions; and

storing the new program counter value in the program counter.

5. The method of claim 1, wherein executing the set of instructions comprises executing a first instruction in a first execution unit and a second instruction in a second execution unit, and wherein the execution of the first and second instructions is in parallel.

6. The method of claim 1, wherein the memory device is a first node of a plurality of memory device nodes, and wherein communicating the packet from the memory processing apparatus comprises transmitting the packet to a second node of the plurality of memory device nodes.

7. The method of claim 1, wherein the set of instructions comprises a fence flag and wherein storing the set of instructions comprises:

storing one or more instructions prior to the fence flag in instruction memory and one or more instructions succeeding the fence flag in the instruction memory.

8. The method of claim 7, further comprising:

executing the one or more instructions prior to the fence flag in a first execution unit; and

executing the one or more instructions after the fence flag in a second execution unit.

9. The method of claim 7, wherein executing the one or more instructions prior to the fence flag is performed simultaneously with executing the one or more instructions after the fence flag.

10. The method of claim 1, wherein executing the set of instructions using the execution unit comprises:

providing a plurality of operands to a program counter execution unit;

providing an operator to the program counter execution unit; and

generating an updated program counter value in response to results from the execution of the operator on the plurality of operands.

11. The method of claim 1, wherein the at least one execution unit, the packet parser, and the packet generator of the memory processing apparatus are located within a same hardware component as the storage memory.

12. The method of claim 1, wherein the memory processing apparatus and the storage memory are included in one of:

a same die, a same die stack, or a same memory module, and wherein the storage memory comprises;

random access memory (RAM), dynamic random access memory (DRAM), synchronous random access memory (SRAM), NAND Flash, NOR Flash, or phase change memory (PCM).

13. The method of claim 1, wherein the memory processing apparatus is one of a plurality of memory processing apparatuses located within the memory device.

14. The method of claim 1, wherein the at least one execution unit comprises:

a plurality of arithmetic logic units (ALUs); and

a multiplexing function coupled between outputs of at least two of the plurality of the ALUs.

15. The method of claim 14, wherein the plurality of ALUs comprises an ALU associated with each instruction from the set of instructions.

16. A memory device comprising:

a storage memory; and

a memory processing apparatus comprising;

an interface to receive a first packet, the first packet including a set of instructions;

a packet parser to parse the first packet to obtain the set of instructions from the first packet;

at least one execution unit to execute the set of instructions to retrieve data from the storage memory of the memory device; and

a packet generator to combine, into a second packet, the set of instructions with the data retrieved from the storage memory, and transmit the second packet from the memory processing apparatus to a memory controller connected to the memory device,

wherein the memory processing apparatus is located within a same hardware component as the storage memory.

17. The memory device of claim 16, wherein the at least one execution unit comprises:

a plurality of arithmetic logic units (ALUs); and

a multiplexing function coupled between outputs of at least two of the plurality of the ALUs.

18. The memory device of claim 17, wherein the plurality of ALUs comprises an ALU associated with each instruction from the set of instructions.

19. The memory device of claim 16, wherein the interface is adapted to receive the first packet via a network coupled to the memory device, and wherein the interface is further adapted to transmit the second packet via the network.

20. The memory device of claim 16, wherein the memory processing apparatus and the storage memory are included in one of:

a same die, a same die stack, or a same memory module, and

wherein the storage memory comprises;

random access memory (RAM), dynamic random access memory (DRAM), synchronous random access memory (SRAM), NAND Flash, NOR Flash, or phase change memory (PCM).

21. The memory device of claim 16, wherein the memory processing apparatus is one of a plurality of memory processing apparatuses located within the memory device.

22. The memory device of claim 16, wherein parsing the first packet to obtain the set of instructions comprises:

loading a program counter with an initial program counter value associated with the set of instructions;

loading an instruction memory with the set of instnictions; and

loading a register file with a set of initial conditions associated with the set of instructions.

23. The memory device of claim 22, wherein executing the set of instructions comprises:

calculating a new program counter value after executing a first instruction of the set of instructions; and

storing the new program counter value in the program counter.

24. The memory device of claim 16, wherein executing the set of instructions comprises executing a first instruction in a first execution unit and a second instruction in a second execution unit, and wherein the execution of the first and second instructions is in parallel.

25. The memory device of claim 16, wherein the memory device is a first node of a plurality of memory device nodes, and wherein the transmitting of the second packet from the memory processing apparatus comprises transmitting the second packet to a second node of the plurality of memory device nodes.

26. The memory device of claim 16, wherein the set of instructions comprises a fence flag and wherein storing the set of instructions comprises:

storing one or more instructions prior to the fence flag in instruction memory and one or more instructions succeeding the fence flag in the instruction memory.

27. The memory device of claim 26, further comprising:

executing the one or more instructions prior to the fence flag in a first execution unit; and

executing the one or more instructions succeeding the fence flag in a second execution unit.

28. The memory device of claim 26, wherein executing the one or more instructions prior to the fence flag is performed simultaneously with executing the one or more instructions succeeding the fence flag.

29. The memory device of claim 16, wherein executing the set of instructions comprises:

providing a plurality of operands to a program counter execution unit;

providing an operator to the program counter execution unit; and

generating an updated program counter value in response to results from the execution of the operator on the plurality of operands.

30. An apparatus, comprising:

a memory device configured to be operably coupled to a memory controller of a host computing system, the memory device comprising a storage memory; and

a memory processing apparatus hosted on a same hardware component as the storage memory, the memory processing apparatus operable to perform operations comprising;

receiving and parsing a set of instructions at the memory processing apparatus, using a packet parser, the set of instructions being received from the memory controller;

executing the set of instructions, using at least one execution unit of the memory processing apparatus, to retrieve data from the storage memory of the memory device;

combining, into a packet using a packet generator of the memory processing apparatus, the set of instructions with the data retrieved from the storage memory; and

communicating the packet from the memory processing apparatus to the memory controller.

31. The apparatus of claim 30, wherein the receiving of the set of instructions comprises receiving the set of instructions via a network coupled to the memory device, and wherein the communicating of the packet comprises transmitting the packet via the network.

32. The apparatus of claim 30, wherein the parsing of the set of instructions comprises parsing a received packet that includes the set of instructions, by:

loading a program counter with an initial program counter value associated with the received set of instructions;

loading an instruction memory with the set of instructions; and

loading a register file with a set of initial conditions associated with the set of instructions.

33. The apparatus of claim 32, wherein executing the set of instructions comprises:

calculating a new program counter value after executing a first instruction of the set of instructions; and

storing the new program counter value e program counter.

34. The apparatus of claim 30, wherein executing the set of instructions comprises executing a first instruction in a first execution unit and a second instruction in a second execution unit, and wherein the execution of the first and second instructions is in parallel.

35. The apparatus of claim 30, wherein the memory device is a first node of a plurality of memory device nodes, and wherein communicating the packet from the memory processing apparatus comprises transmitting the packet to a second node of the plurality of memory device nodes.

36. The apparatus of claim 30, wherein the set of instructions comprises a fence flag and wherein storing the set of instructions comprises:

storing one or more instructions prior to the fence flag in instruction memory and one or more instructions succeeding the fence flag in the instruction memory.

37. The apparatus of claim 36, further comprising:

executing the one or more instructions prior to the fence flag in a first execution unit; and

executing the one or more instructions succeeding the fence flag in a second execution unit.

38. The apparatus of claim 36, wherein executing the one or more instructions prior to the fence flag is performed simultaneously with executing the one or more instructions succeeding the fence flag.

39. The apparatus of claim 30, wherein executing the set of instructions using the execution unit comprises:

providing a plurality of operands to a program counter execution unit;

providing an operator to the program counter execution unit; and

generating an updated program counter value in response to results from the execution of the operator on the plurality of operands.

40. The apparatus of claim 30, wherein the memory processing apparatus and the storage memory are included in one of:

a same die, a same die stack, or a same memory module, and wherein the storage memory comprises;

random access memory (RAM), dynamic random access memory (DRAM), synchronous random access memory (SRAM), NAND Flash, NOR Flash, or phase change memory (PCM).

41. The apparatus of claim 30, wherein the memory processing apparatus is one of a plurality of memory processing apparatuses located within the memory device.

42. The apparatus of claim 30, wherein the at least one execution unit comprises:

a plurality of arithmetic logic units (ALUs); and

a multiplexing function coupled between outputs of at least two of the plurality of the ALUs.

43. The apparatus of claim 42, wherein the plurality of ALUs comprises an ALU associated with each instruction from the set of instructions.