Multiple column per channel CCD sensor architecture for inspection and metrology

• US 10,778,925 B2
• Filed: 06/12/2019
• Issued: 09/15/2020
• Est. Priority Date: 04/06/2016
• Status: Active Grant

• Current Assignee: KLA-Tencor Corporation
• Original Assignee: KLA-Tencor Corporation
• Inventors: Chuang, Yung-Ho Alex, Zhang, Jingjing, Zamek, Sharon, Fielden, John, Contarato, Devis, Brown, David L.
• Primary Examiner(s): Hilaire, Clifford
• Application Number:
  US16/439,297
• Publication Number:
  US 20190313044A1
• Time in Patent Office: 461 Days
• Field of Search: None
• CPC Class Codes: G01N 2021/95676 Masks, reticles, shadow masks
• CPC Class Codes: G01N 21/9501 Semiconductor wafers manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G01N 21/956 Inspecting patterns on the surface of objects contactless testing of electronic circuits G01R31/308; testing currency G07D; manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/0008 checking presence/absence
• CPC Class Codes: H01L 27/14812 Special geometry or disposition of pixel-elements, address lines or gate-electrodes
• CPC Class Codes: H01L 27/14825 Linear CCD imagers
• CPC Class Codes: H01L 27/14831 Area CCD imagers
• CPC Class Codes: H01L 29/76816 Output structures
• CPC Class Codes: H04N 25/63 applied to dark current
• CPC Class Codes: H04N 25/71 Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
• CPC Class Codes: H04N 25/713 Transfer or readout registers; Split readout registers or multiple readout registers
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array

Abstract

A multiple-column-per-channel image CCD sensor utilizes a multiple-column-per-channel readout circuit including connected transfer gates that alternately transfer pixel data (charges) from a group of adjacent pixel columns to a shared output circuit at high speed with low noise. Charges transferred along the adjacent pixel columns at a line clock rate are alternately passed by the transfer gates to a summing gate that is operated at multiple times the line clock rate to pass the image charges to the shared output circuit. A symmetrical fork-shaped diffusion is utilized in one embodiment to merge the image charges from the group of related pixel columns. A method of driving the multiple-column-per-channel CCD sensor with line clock synchronization is also described. A method of inspecting a sample using the multiple-column-per-channel CCD sensor is also described.

Claims

1. A multiple-column-per-channel charge-coupled-device (CCD) image sensor comprising:

a pixel array including a plurality of pixels arranged in a plurality of columns and a plurality of pixel rows, the pixel array being configured to generate image charges and to sequentially transfer each said image charge between associated pixels disposed in a corresponding said column in response to a plurality of pixel control signals, whereby a set of image charges disposed in a first said pixel row is simultaneously transferred to an adjacent second said pixel row during each cycle of said plurality of pixel control signals;

a readout circuit comprising;

a plurality of buffer cells disposed to simultaneously receive image charges from an edge pixel row in response to one or more buffer control signals such that each buffer cell receives a corresponding image charge from an associated pixel of said edge pixel row upon assertion of said one or more buffer control signals;

a plurality of transfer gates disposed in said plurality of columns and arranged in a plurality of transfer gate rows including a first transfer gate row disposed to receive a corresponding image charge from an associated said buffer cell, each of said plurality of transfer gates being operably controlled by and associated transfer clock signal;

a summing gate coupled to a last transfer gate row; and

an output circuit coupled to the summing gate,

wherein said plurality of transfer gates are configured and coupled such that asserting a first transfer clock signal during a first time periodcauses a first image charge to be transferred from a first said buffer cell to a first transfer gate, and causes a second image charge to be transferred from a second said transfer gate to a third said transfer gate,

wherein said first buffer cell and said first transfer gate are disposed in a first said column, and said second transfer gate and said third transfer gate are disposed in a second said column, and

wherein the summing gate is configured to receive the second image charge from the second column during a second time period subsequent to the first time period in accordance with a summing gate control signal, and the summing gate is further configured to receive the first image charge from the first column during a third time period subsequent to the second time period in accordance with the summing gate control signal and

wherein a clock rate of the summing gate control signal is at least two times faster than a line clock rate of the plurality of pixel control signals.

2. The sensor of claim 1,

wherein said plurality of transfer gates are further configured such that asserting said first transfer clock signal during said first time periodfurther causes a third image charge to be transferred from a fourth said transfer gate to a fifth said transfer gate,

wherein said fourth transfer gate and said fifth transfer gate are disposed in a third said column, and

wherein said first transfer gate and said fourth transfer gate are disposed in said first transfer gate row, said second transfer gate and said fifth transfer gate are disposed in a second transfer gate row disposed below the first transfer gate row, and said third transfer gate is disposed in a third transfer gate row disposed below the second transfer gate row.

3. The sensor of claim 1, wherein the output circuit comprises a floating diffusion configured to receive and store said image charges, and an amplifier coupled to the floating diffusion and configured to generate a corresponding output voltage signal in accordance with each said image charge stored on the floating diffusion.

4. The sensor of claim 1, wherein the readout circuit includes a plurality of readout structures, each said readout structure connected to an associated group of said columns and includes a corresponding plurality of said transfer gates, a corresponding said summing gate, and a corresponding said output circuit.

5. The sensor of claim 4, wherein said amplifier of each said readout structure comprises a metal interconnect, wherein capacitances of the metal interconnects of different amplifiers are substantially similar.

6. The sensor of claim 4, wherein each said amplifier comprises a metal interconnect, wherein areas of the metal interconnects of different amplifiers are substantially similar.

7. The sensor of claim 4, wherein the array of pixels consists of one or more rows of pixels.

8. The sensor of claim 2, wherein the sensor further comprises an output control circuit configured to operably control the summing gate such that a fourth image charge is transferred from a sixth said transfer gate to said summing gate during the first time period, wherein said sixth transfer gate is disposed in said first column and disposed in said third transfer gate row.

9. The sensor of claim 8, wherein said plurality of transfer gates are further configured such that asserting a second transfer clock signal during a second time periodcauses a fourth image charge to be transferred from a second said buffer cell to a seventh said transfer gate, causes said first image charge to be transferred from said first transfer gate to an eighth said transfer gate, and causes said third image charge to be transferred from said fifth said transfer gate to a ninth said transfer gate,

wherein the said second buffer cell is disposed in said third column,

wherein said seventh transfer gate is disposed in said second column and said first transfer gate row,

wherein said eighth transfer gate is disposed in said first column and said second transfer gate row, and

wherein said ninth transfer gate is disposed in said third column and said third transfer gate row.

10. The sensor of claim 9, wherein the output control circuit is further configured to operably control the output circuit and the summing gate such that said fourth image charge is transferred from said summing gate to a floating diffusion and said second image charge is transferred from said third transfer gate to said summing gate during the second time period.

11. The sensor of claim 10, wherein said plurality of transfer gates are further configured such that asserting a third transfer clock signal during a third time periodcauses a sixth image charge to be transferred from a third said buffer cell to said fourth transfer gate, causes said first image charge to be transferred from said eighth transfer gate to said sixth transfer gate, and causes said fourth image charge to be transferred from said seventh transfer gate to said second transfer gate.

12. The sensor of claim 11, wherein the output control circuit is further configured to operably control the output circuit and the summing gate such that said second image charge is transferred from said summing gate to said floating diffusion and said third image charge is transferred from said ninth transfer gate to said summing gate during the third time period.

13. The sensor of claim 12, further comprising a buffer control circuit configured to control the first, second and third buffer cells to simultaneously respectively receive seventh, eighth and ninth image charges from said edge pixel row during the third time period and after the sixth image charge is transferred from said third said buffer cell to said fourth transfer gate.

14. A method of inspecting a sample, the method comprising:

directing and focusing radiation onto the sample while moving the sample relative to a source of said radiation;

directing received radiation from the sample to an image sensor, the image sensor comprising a multiple-column-per-channel charge-coupled-device (CCD) including an array of pixels arranged in a plurality of rows and a plurality of associated groupsof adjacent columns, each said associated group including at least a first column a second column and a third column;

driving the image sensor with line clock signals that are synchronized to said moving of the sample relative to the radiation source, the line clock signals causing first and second charges to be respectively transferred along the first, second and third columns from one said row of pixels to an adjacent said row of pixels;

driving a row of buffer cells of the image sensor with a buffer clock signal, the buffer clock signal causing said first and second charges to be respectively transferred from an edge pixel row of pixels in the first, second and third columns of each associated group of columns to first, second and third buffer cells of the row of buffer cells;

simultaneously driving with a first transfer clock signal during a first time period a first transfer gate, a third transfer gate and a fifth transfer gate, said first transfer gate being disposed in a first row of said transfer gates and disposed in the first column, the third transfer gate being disposed in a third row of said transfer gates and disposed in the second column, and the fifth transfer gate being disposed in a second row of said transfer gates and disposed in the third column,

simultaneously driving with a second transfer clock signal during a second time period a seventh transfer gate, an eighth transfer gate and a ninth transfer gate, said seventh transfer gate being disposed in the first row of said transfer gates and disposed in the second column, the eighth transfer gate being disposed in said second row of said transfer gates and disposed in the first column, and the ninth transfer gate being disposed in the third row of said transfer gates and disposed in the third column,

simultaneously driving with a third transfer clock signal during a third time period a fourth transfer gate, a second transfer gate and a sixth transfer gate, said fourth transfer gate being disposed in the first row of said transfer gates and disposed in the third column, the second transfer gate being disposed in said second row of said transfer gates and disposed in the second column, and the sixth transfer gate being disposed in the third row of said transfer gates and disposed in the first column,

utilizing an output circuit and an analog-to-digital converter (ADC) circuit to sequentially convert image charges transferred along the first, second and third columns to digital numbers,

wherein utilizing the ADC circuit includes driving the ADC circuit with a clock frequency greater than at least three times a frequency of the line clock signals.

15. The method of claim 14, wherein simultaneously driving with said first transfer clock signal comprises asserting the first transfer clock signal such that a first image charge is transferred from said first buffer cell to said first transfer gate, causes a second image charge to be transferred from said second transfer gate to said third transfer gate, and causes a third image charge to be transferred from said fourth transfer gate to said fifth transfer gate during the first time period.

16. The method of claim 15, wherein utilizing said output circuit comprises controlling a summing gate such that a fourth image charge is transferred from said sixth transfer gate to said summing gate during the first time period.

17. The method of claim 16, wherein simultaneously driving with said second transfer clock signal comprises asserting the second transfer clock signal such that a fourth image charge is transferred from said second buffer cell to said seventh transfer gate, said first image charge is transferred from said first transfer gate to said eighth transfer gate, and said third image charge is transferred from said fifth transfer gate to said transfer gate during said second time period.

18. The method of claim 17, wherein utilizing said output circuit further comprises controlling said summing gate and a sense node such that said fourth image charge is transferred from said summing gate to a floating diffusion and said second image charge is transferred from said third transfer gate to said summing gate during the second time period.

19. The method of claim 18, wherein simultaneously driving with said third transfer clock signal comprises asserting the third transfer clock signal such that during said third time period a sixth image charge is transferred from said third buffer cell to said fourth transfer gate, said first image charge is transferred from said eighth transfer gate to said sixth transfer gate, and said fourth image charge is transferred from said seventh transfer gate to said second transfer gate.

20. The method of claim 19, wherein utilizing said output circuit further comprises controlling said summing gate and said sense node such that said second image charge is transferred from said summing gate to said floating diffusion and said third image charge is transferred from said ninth transfer gate to said summing gate during the third time period.

21. The method of claim 20, further comprises driving said row of buffer cells such that the first, second and third buffer cells simultaneously respectively receive seventh, eighth and ninth image charges from said edge pixel row during the third time period and after the sixth image charge is transferred from said third said buffer cell to said fourth transfer gate.