Methods of forming backside self-aligned vias and structures formed thereby

• US 10,797,139 B2
• Filed: 06/28/2019
• Issued: 10/06/2020
• Est. Priority Date: 09/24/2015
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Morrow, Patrick, Kobrinsky, Mauro J., Jun, Kimin, Son, Il-Seok, Fischer, Paul B.
• Primary Examiner(s): Yushin, Nikolay K
• Application Number:
  US16/457,728
• Publication Number:
  US 20190326405A1
• Time in Patent Office: 466 Days
• CPC Class Codes: H01L 21/02529 Silicon carbide
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41775 : characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/41791 : for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6656 : using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66636 : with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 : with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 : the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 : with the body tied to the substrate

Abstract

Methods and structures formed thereby are described, of forming self-aligned contact structures for microelectronic devices. An embodiment includes forming a trench in a source/drain region of a transistor device disposed in a device layer, wherein the device layer is on a substrate, forming a fill material in the trench, forming a source/drain material on the fill material, forming a first source/drain contact on a first side of the source/drain material, and then forming a second source drain contact on a second side of the source/drain material.

Claims

1. A microelectronic device structure, comprising:

a fin of monocrystalline semiconductor material over a dielectric material

a gate electrode adjacent to the fin;

a drain region adjacent to the fin;

a first contact to the drain region, the first contact adjacent to the gate electrode;

a source region adjacent to the fin, and opposite the drain region;

a second contact to the source region, the second contact adjacent to the gate electrode; and

a third contact adjacent to the dielectric material, and in contact with the source region or the drain region, wherein the third contact is opposite the first contact or the second contact.

2. The microelectronic device structure of claim 1, wherein:

the third contact is separated from the first or second contact by only the source region or drain region.

3. The microelectronic device structure of claim 1, wherein

the fin comprises silicon and the source region and the drain region both comprise at least one of silicon and germanium.

4. The microelectronic device structure of claim 1, wherein the third contact comprises at least one of copper, tungsten, cobalt, or titanium.

5. The microelectronic device structure of claim 1, further comprising first interconnects coupled to the first and second contact, and second interconnects coupled to the third contact, wherein the first interconnects are over the fin and the second interconnects are under the fin.

6. A system comprising:

circuitry comprising the microelectronic device structure of claim 1; and

a DRAM communicatively coupled to circuitry.

7. The microelectronic device structure of claim 1, wherein:

the first contact and the second contact are separated from the gate electrode by an intervening spacer dielectric material; and

the third contact has a first length from the dielectric material that is substantially equal to a first length of the first or second contact from the dielectric spacer material.

8. The microelectronic device structure of claim 7, wherein:

the source region and drain region have a second length, orthogonal to, but in the plane of, the first length that exceeds a transverse width of the fin; and

the third contact also has a second length that exceeds the transverse width of the fin.

9. A microelectronic device structure, comprising:

a first transistor, comprising;

a first fin of monocrystalline semiconductor material, the first fin over a dielectric material

a first gate electrode adjacent to a sidewall of the first fin;

a first source/drain region adjacent to the first fin;

a first contact to the first source/drain region, the first contact adjacent to the first gate electrode;

a second source/drain region adjacent to the first fin;

a second contact to the second source/drain region, the second contact adjacent to the first gate electrode; and

a third contact adjacent to the dielectric material, and in contact with the first source/drain region, opposite the first source/drain region; and

a second transistor, comprising;

a second fin of the monocrystalline semiconductor material, the second fin over the dielectric material;

a second gate electrode adjacent to the second fin;

a third source/drain region adjacent to the fin;

a fourth contact to the third source/drain region, the fourth contact adjacent to the second gate electrode;

a fourth source/drain region adjacent to the fin;

a fifth contact to the fourth source/drain region, the fifth contact adjacent to the second gate electrode; and

a sixth contact adjacent to the dielectric material, and in contact with the fourth source/drain region, opposite the fourth source/drain region, wherein the third contact is separated from the sixth contact by the dielectric material.

10. The microelectronic device structure of claim 9, wherein:

the third contact is in contact with the dielectric material, and is separated from the first contact by only the first source/drain region; and

the sixth contact is in contact with the dielectric material, and is separated from the fifth contact by only the fourth source/drain region.

11. The microelectronic device structure of claim 9, wherein

the first and second fin comprises silicon and the source region and the drain region both comprise at least one of silicon and germanium.

12. The microelectronic device structure of claim 9, wherein the third contact and the sixth contact both comprise at least one of copper, tungsten, cobalt, or titanium.

13. The microelectronic device structure of claim 9, further comprising:

first interconnects coupled to the first, second, fourth and fifth contacts, wherein the first interconnects are over the first and second fins; and

second interconnects coupled to the third and sixth contacts, wherein the second interconnects are under the first and second fins.

14. The microelectronic structure of claim 9, wherein:

a first vertical height of the first, second, fourth and fifth contacts is substantially the same;

a second vertical height of the third and sixth contacts is substantially the same; and

the second vertical height is less than the first vertical height.

15. The microelectronic structure of claim 14, wherein the first vertical height is at least twice the second vertical height.

16. A method of forming a microelectronic structure, the method comprising:

forming a gate electrode over a sidewall of a fin, the fin comprising a monocrystalline semiconductor material;

forming a trench adjacent to the gate electrode to a depth below the gate electrode;

forming a first contact within the trench;

forming a source/drain region in contact with the fin and over the first contact;

forming a second contact to the source/drain region, the second contact opposite the first contact, and adjacent to the gate electrode.

17. The method of claim 16, further comprising forming a first interconnect layer coupled to the first contact, and forming a second interconnect layer coupled to the second contact.

18. The method of claim 16, wherein forming the source/drain region further comprises epitaxially growing a material comprising at least one of silicon or germanium after forming the first contact.

19. The method of claim 16, wherein forming the first contact comprises at least partially backfilling the trench with a conductive material comprising a metal.

20. The method of claim 19, wherein the metal comprises at least one of copper, tungsten, cobalt, or titanium.