Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink

• US 10,797,691 B1
• Filed: 04/20/2020
• Issued: 10/06/2020
• Est. Priority Date: 07/11/2005
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Inventors: Brindle, Christopher N., Stuber, Michael A., Kelly, Dylan J., Kemerling, Clint L., Imthurn, George, Welstand, Robert B., Burgener, Mark L.
• Primary Examiner(s): Nguyen, Niki H
• Application Number:
  US16/853,688
• Publication Number:
  US 20200295751A1
• Time in Patent Office: 169 Days
• Field of Search: 257105, 257 40, 257347, 257402, 257403, 455333, 455425, 455550
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78615 with a body contact
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

Claims

1. A method of fabricating an RF switch comprising:

fabricating an integrated circuit (IC) that includes the RF switch;

wherein the fabricating includes forming at least a plurality of N-type metal oxide semiconductor field effect transistors (NMOSFETs) by forming a source, a drain, a gate and a body for respective NMOSFETs of the plurality in a silicon layer of a substrate;

wherein the fabricating further includes fabricating one or more layers of metallization over the silicon layer;

wherein the one or more layers of metallization to couple the plurality of NMOSFETs into a stack to pass an RF signal through the stack of NMOSFETs in an ON state of the stack of NMOSFETs in accordance with RF switch operation;

wherein the one or more layers of metallization to couple the plurality of NMOSFETs of the stack to not pass an RF signal through the stack of NMOSFETs in an OFF state of the stack of NMOSFETs in accordance with RF switch operation; and

wherein the one or more layers of metallization to couple an electrical bias to the body of the respective NMOSFETs, in accordance with RF switch operation, at least in a portion of the OFF state of the stack to have a DC voltage level substantially more negative than a lowest voltage level of the following;

ground, a DC voltage level of the source of the respective NMOSFETs, and a DC voltage level of the drain of the respective NMOSFETs.

2. The method of claim 1, wherein the substrate comprises a silicon on insulator (SOI) substrate.

3. The method of claim 2, wherein the forming the source, the drain, the gate and the body for the respective NMOSFETs of the plurality in the silicon layer of the SOI substrate comprises:

forming the gate from a conductive layer and an oxide layer on the silicon layer of the SOI substrate; and

forming two N+ regions in the silicon layer of the SOI substrate via ion implantation or diffusion to form the source, the drain, and the body.

4. The method of claim 2, wherein the forming the gate from the conductive layer comprises forming the gate from a polysilicon gate layer.

5. The method of claim 3, wherein the silicon layer of the SOI substrate comprises a thin-film silicon layer with a thickness of less than 150 nm.

6. The method of claim 5, wherein the forming the two N+ regions comprises forming the two N+ regions to extend through the silicon layer to an insulating layer of the SOI substrate.

7. The method of claim 2, wherein the fabricating further includes forming an accumulated charge sink (ACS) in direct physical contact with the body of the respective NMOSFETs, the ACS being formed in the silicon layer.

8. The method of claim 7, wherein the fabricating further includes forming an electrical contact region for the ACS, the electrical contact region comprising a P+ doped region formed in the silicon layer via ion implantation or diffusion.

9. The method of claim 8, wherein the electrical contact region for the ACS is formed in the silicon layer a selected distance away from the body of the respective NMOSFETs.

10. The method of claim 7, wherein the fabricating further includes fabricating a diode in the silicon layer of the SOI substrate and wherein at least one of the fabricated layers of metallization over the silicon layer couples the diode to the ACS, for the respective NMOSFETs.

11. The method of claim 2, wherein the fabricating comprises fabricating a negative voltage generator circuit to generate the DC voltage level to have the voltage level substantially more negative than the lowest voltage level of the following:

ground, the DC voltage level of the source of the respective NMOSFETs, and the DC voltage level of the drain for the respective NMOSFETs.

12. The method of claim 11, wherein the fabricating the negative voltage generator circuit comprises fabricating the negative voltage generator circuit to comprise a charge pump.

13. The method of claim 11, wherein the fabricating the negative voltage generator comprises fabricating the negative voltage generator circuit to generate the DC voltage level to have the voltage level at least one volt more negative than the lowest voltage level of the following:

ground, the DC voltage level of the source for the respective NMOSFETs, and the DC voltage level of the drain for the respective NMOSFETs.