SPAD detector having modulated sensitivity

• US 10,801,886 B2
• Filed: 01/24/2018
• Issued: 10/13/2020
• Est. Priority Date: 01/25/2017
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Mandai, Shingo, McMahon, Andrew Kenneth John, Niclass, Cristiano L., Oggier, Thierry, Kaitz, Tal, Laifenfeld, Moshe
• Primary Examiner(s): Sohn, Seung C
• Application Number:
  US15/879,365
• Publication Number:
  US 20180209846A1
• Time in Patent Office: 993 Days
• Field of Search: 250207, 2502081
• CPC Class Codes: G01J 1/4228 arrangements with two or more detectors, e.g. for sensitivity compensation
• CPC Class Codes: G01J 1/44 Electric circuits for command of an exposure part G03B7/02
• CPC Class Codes: G01J 2001/442 Single-photon detection or photon counting
• CPC Class Codes: G01J 2001/4466 Avalanche
• CPC Class Codes: G01S 17/08 for measuring distance only indirect measurement G01S17/46; active triangulation systems G01S17/48
• CPC Class Codes: G01S 17/894 3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar
• CPC Class Codes: G01S 7/4863 Detector arrays, e.g. charge-transfer gates
• CPC Class Codes: G01S 7/4865 Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak peak detection in noise, signal conditioning G01S7/487
• CPC Class Codes: G01S 7/4868 Controlling received signal intensity or exposure of sensor

Abstract

The sensitivity of one or more single-photon avalanche diodes (SPAD) in a SPAD detector is modulated over time. The sensitivity of all of the SPADs may be modulated, or the sensitivity of one section of the SPADs can be modulated differently from another section of the SPADs. Various techniques for modulating the sensitivity are disclosed.

Claims

1. A single-photon avalanche diode (SPAD) detector, comprising:

a pixel array comprising multiple lines of pixels, each pixel comprising a SPAD;

a time-to-digital converter (TDC) array circuit operably connected to the pixel array, the TDC array circuit comprising an array of TDC circuits with a subset of the TDC circuits operably connected to each respective line of pixels; and

a memory operably connected to the TDC array circuit, the memory configured to store a non-uniform histogram that comprises;

a first bin having a first width, the first bin representing a first count of photons having times of flight within a first range of times of flight; and

a second bin having a second width different from the first width, the second bin representing a second count of photons having times of flight within a second range of times of flight different from the first range of times of flight, wherein the first bin provides the SPAD detector with a first sensitivity to photons and the second bin provides the SPAD detector with a second sensitivity to photons that is different from the first sensitivity.

2. The SPAD detector of claim 1, further comprising a controller operably connected to the TDC array circuit, the controller configured to generate clock signals for the TDC array circuit.

3. The SPAD detector of claim 1, wherein:

the SPAD detector is included in a line scan system;

the multiple lines of pixels in the pixel array are arranged in rows and columns;

the pixels in the pixel array are scanned in sections, each section including a subset of the columns in the pixel array; and

a number of TDC circuits in each subset of the TDC circuits correspond to a subset of scanned pixels in each row in each section.

4. The SPAD detector of claim 3, wherein:

the pixel array comprises;

a reference sub-array comprising reference pixels; and

an imaging sub-array comprising imaging pixels; and

the SPAD detector further comprises a controller operably connected to the TDC array circuit, the controller configured to;

produce a first set of clock signals comprising a first clock signal having a first phase and a second clock signal having a different second phase; and

produce a second set of clock signals comprising a third clock signal having a third phase and a fourth clock signal having a different fourth phase;

the first set of clock signals is received by the TDC circuits connected to the reference pixels; and

the second set of clock signals is received by the TDC circuits connected to the imaging pixels.

5. The SPAD detector of claim 3, wherein the memory is configured to store multiple non-uniform histograms and each non-uniform histogram is associated with each scanned pixel in each row of each section.

6. The SPAD detector of claim 1, wherein the pixel array comprises:

a reference sub-array comprising one or more reference pixels; and

an imaging sub-array comprising one or more imaging pixels.

7. The SPAD detector of claim 6, wherein each imaging pixel in the imaging sub-array comprises:

a SPAD operably connected between a node and a first voltage supply;

a gating transistor operably connected between the node and a reference voltage supply; and

a quenching transistor operably connected between the node and a second voltage supply, wherein

the gating transistor is configured to enable an operation of the SPAD or disable the operation of the SPAD.

8. The SPAD detector of claim 6, wherein each TDC circuit operably connected to each imaging pixel outputs multiple TDC output values for the imaging pixel and the multiple TDC output values increase non-uniformly over a detection period of the imaging pixel.

9. The SPAD detector of claim 6, further comprising an encoder circuit operably connected between the TDC array circuit and the memory, wherein:

each TDC circuit operably connected to a respective imaging pixel outputs multiple TDC output values for the imaging pixel and the multiple TDC output values increase linearly over a detection period of the imaging pixel; and

the encoder circuit is configured to encode the multiple TDC output values such that the multiple encoded TDC output values increase non-uniformly over the detection period of the imaging pixel.

10. The SPAD detector of claim 6, wherein the reference sub-array is positioned adjacent to an edge of the imaging sub-array.

11. The SPAD detector of claim 1, wherein the non-uniform histogram further comprises:

a third bin having a third width different from the first width and the second width, the third bin representing a third count of photons having times of flight within a third range of times of flight different from both the first range of times of flight and the second range of times of flight, the third bin providing the SPAD detector with a third sensitivity to photons that is different from each of the first sensitivity and the second sensitivity.

12. A pixel in a single-photon avalanche diode (SPAD) detector, the pixel comprising:

a SPAD operably connected between a node and a first voltage supply;

a gating transistor operably connected between the node and a reference voltage supply; and

a quenching transistor operably connected between the node and a second voltage supply, wherein

the gating transistor is configured to receive a gating signal that enables an operation of the SPAD at a first time and subsequently disables the operation of the SPAD at a second time;

a gate of the quenching transistor is connected to a first switch and a second switch;

the first switch is connected to a first quenching signal; and

the second switch is connected to a second quenching signal that is different from the first quenching signal.

13. The pixel of claim 12, wherein a time interval between the first time and the second time determines a detection period for the SPAD during which the SPAD detects photons.

14. The pixel of claim 12, wherein:

the first quenching signal produces a sensitivity-controlled period in the SPAD, the SPAD having a variable sensitivity during the sensitivity-controlled period; and

the second quenching signal produces a constant sensitivity period in the SPAD.

15. The pixel of claim 12, further comprising a select transistor operably connected between the quenching transistor and the gating transistor, wherein a gate of the select transistor and a gate of the gating transistor are connected to a common input line.

16. A single-photon avalanche diode (SPAD) detector, comprising:

a pixel array comprising a plurality of pixels arranged in a reference sub-array and an imaging sub-array, each pixel comprising a SPAD and a quenching transistor operably connected to the SPAD;

a constant voltage source operably connected to a terminal of each quenching transistor in the reference sub-array;

a switch array operably connected to the pixel array, wherein each switch in the switch array is connected to a respective line of pixels in the imaging sub-array; and

a variable signal source operably connected to a terminal of each quenching transistor in the pixels in each line of pixels in the imaging sub-array through a respective switch in the switch array.

17. The SPAD detector of claim 16, wherein the variable signal source comprises a digital-to-analog converter operably connected to a variable voltage input signal.

18. The SPAD detector of claim 16, wherein the variable signal source comprises a single-slope voltage ramp generator.

19. A single-photon avalanche diode (SPAD) detector, comprising:

a pixel array comprising a plurality of pixels, each pixel comprising a SPAD and a quenching transistor operably connected to the SPAD;

a switch array operably connected to the pixel array;

a current source operably connected to a gate of each quenching transistor in each line of pixels in the pixel array through a respective first switch in the switch array; and

a variable signal generator operably connected to a terminal of each quenching transistor in each line of pixels in the pixel array through a respective second switch in the switch array.

20. The SPAD detector of claim 19, wherein the current source is a global current source.

21. A method for operating a single-photon avalanche diode (SPAD) detector, the SPAD detector comprising a pixel array that includes a reference sub-array of reference pixels and an imaging sub-array of imaging pixels, the method comprising:

detecting a start time to enable an operation of an imaging SPAD in an imaging pixel in the imaging sub-array using a reference SPAD in a reference pixel in the reference sub-array;

in response to detecting the start time, enabling the operation of the imaging SPAD such that the imaging SPAD is operable to detect photons;

determining, for each detected photon, a respective time of flight; and

constructing a non-uniform histogram based on a time of flight of each detected photon, wherein the non-uniform histogram comprises;

a first bin having a first width, the first bin representing a first count of photons having times of flight within a first range of times of flight; and

a second bin having a second width different from the first width, the second bin representing a second count of photons having times of flight within a second range of times of flight different from the first range of times of flight, the first bin providing the SPAD detector with a first sensitivity to photons and the second bin providing a second sensitivity to photons that is different from the first sensitivity.

22. The method of claim 21, further comprising disabling the operation of the imaging SPAD after construction of the non-uniform histogram.

23. The method of claim 21, wherein:

the first sensitivity is greater than the second sensitivity;

a first time of flight of a detected first photon that reflects off a first target that is closer to the SPAD detector increments the first count in the first bin; and

a second time of flight of a detected second photon that reflects off a second target that is farther from the SPAD detector increments the second count in the second bin.