Methods and systems for writing to magnetic memory devices utilizing alternating current

• US 10,803,916 B2
• Filed: 12/29/2017
• Issued: 10/13/2020
• Est. Priority Date: 12/29/2017
• Status: Active Grant

• Current Assignee: Integrated Silicon Solution Incorporated (Uphill Investment Co.)
• Original Assignee: Spin Memory, Inc.
• Inventors: Bozdag, Kadriye Deniz, Gajek, Marcin, Tzoufras, Michail, Ryan, Eric Michael
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US15/859,256
• Publication Number:
  US 20190206472A1
• Time in Patent Office: 1,019 Days
• Field of Search: 365158
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/5607 using magnetic storage elements
• CPC Class Codes: H01F 10/3286 Spin-exchange coupled multilayers having at least one layer with perpendicular magnetic anisotropy
• CPC Class Codes: H01F 10/329 Spin-exchange coupled multilayers wherein the magnetisation of the free layer is switched by a spin-polarised current, e.g. spin torque effect
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/85 Magnetic active materials

Abstract

A method for selectively writing to STT-MRAM using an AC current is provided. The method is performed in a memory device including two or more multilevel magnetic tunnel junctions (MTJs) arranged in series with respect to a single terminal of a transistor, where the two or more multilevel MTJs include a first MTJ having a first magnetic characteristic and first electrical characteristic and a second MTJ having a second magnetic characteristic that is distinct from the first magnetic characteristic and a second electrical characteristic. The method includes writing to an MTJ. The writing includes applying a DC current to the two or more MTJs and applying an AC current to the two or more MTJs, where the AC current is adjusted to a frequency that is tuned to a write assist frequency corresponding to the respective MTJ.

Claims

1. A method comprising:

in a memory device including two or more magnetic tunnel junctions (MTJs) including a first magnetic tunnel junction (MTJ) and a second MTJ arranged in series with respect to a single terminal of a transistor, wherein;

the first MTJ has a first magnetic anisotropy and the second MTJ has a second magnetic anisotropy distinct from the first magnetic anisotropy;

the first MTJ has a first write assist frequency and the second MTJ has a second write assist frequency that is distinct from the first write assist frequency;

the first write assist frequency is based on the first magnetic anisotropy; and

the second write assist frequency is based on the second magnetic anisotropy;

writing to a respective MTJ of the first MTJ and the second MTJ, including;

applying a DC current through the first MTJ and the second MTJ arranged in series with respect to the single terminal of the transistor; and

applying an AC current to the first MTJ and the second MTJ, wherein the AC current is adjusted to a frequency that is tuned to a write assist frequency corresponding to the respective MTJ; and

rewriting an initial value of a bit stored in the respective MTJ to a desired value of the bit, including;

identifying the respective MTJ that is storing the initial value of the bit as the first MTJ;

adjusting the AC current to a first AC current having a frequency that is tuned to the first write assist frequency corresponding to the first MTJ;

applying the first AC current to the two or more MTJs;

applying the DC current to the two or more MTJs; and

changing the initial value of the bit to the desired value of the bit by changing a magnetic state of the first MTJ without changing the magnetic state of the second MTJ.

2. The method of claim 1, wherein:

the two or more MTJs are perpendicular MTJs; and

a perpendicular MTJ of the two or more MTJs comprises;

a magnetic reference layer in a first plane, the magnetic reference layer having a magnetization vector that is perpendicular to the first plane and having a fixed magnetization direction;

a non-magnetic spacer layer in a second plane and disposed over the magnetic reference layer; and

a magnetic storage layer in a third plane and disposed over the non-magnetic spacer layer, the magnetic storage layer having a magnetization vector that is perpendicular to the third plane and having a magnetization direction that is same as the magnetic reference layer or that is in the opposite direction of the magnetic reference layer.

3. The method of claim 1, wherein the write assist frequency for the respective MTJ is within 20% of a natural precession frequency of a free layer of the respective MTJ determined while the free layer is in an equilibrium position.

8. The method of claim 1, wherein:

the respective MTJ is the first MTJ; and

applying the AC current to the two or more MTJs comprises applying the AC current adjusted to the write assist frequency of the first MTJ to the two or more MTJs.

9. The method of claim 8, wherein applying the AC current adjusted to the write assist frequency of the first MTJ to the two or more MTJs writes the first MTJ without writing the second MTJ.

10. The method of claim 1, wherein the write assist frequency corresponding to the respective MTJ is determined based on a respective magnetic characteristic of the respective MTJ.

11. The method of claim 1, wherein writing the first MTJ changes a magnetic state of the first MTJ from a first magnetic state to a second magnetic state.

12. The method of claim 11, wherein the first magnetic state of the respective MTJ can be a parallel magnetic state or an anti-parallel magnetic state.

13. The method of claim 11, wherein changing the magnetic state of the respective MTJ from the first magnetic state to the second magnetic state changes a resistance of the respective MTJ.

14. The method of claim 1, further comprising:

after changing the initial value of the bit to the desired value of the bit;

adjusting the AC current to a second AC current having a frequency that is tuned to the second write assist frequency corresponding to the second MTJ, wherein the second AC current is distinct from the first AC current;

applying the second AC current to the two or more MTJs; and

applying a second DC current to the two or more MTJs;

wherein applying the second AC current and the second DC current to the two or more MTJs changes the second MTJ from a first magnetic state to a second magnetic state without changing the magnetic state of the first MTJ.

4. A method comprising:

in a memory device including two or more magnetic tunnel junctions (MTJs) including a first magnetic tunnel junction (MTJ) and a second MTJ arranged in series with respect to a single terminal of a transistor, wherein;

the first MTJ has a first magnetic characteristic and a first electrical characteristic; and

the second MTJ has a second magnetic characteristic that is distinct from the first magnetic characteristic and a second electrical characteristic;

writing to a respective MTJ of the first MTJ and the second MTJ, including;

applying a DC current through the first MTJ and the second MTJ arranged in series with respect to the single terminal of the transistor; and

applying an AC current to the first MTJ and the second MTJ, wherein the AC current is adjusted to a frequency that is tuned to a write assist frequency corresponding to the respective MTJ, wherein;

the first MTJ has a first size and the second MTJ has a second size;

the first MTJ has a first Resistance-Area (RA) product and the second MTJ has a second RA product;

the first electrical characteristic is based on the first RA product and the first size of the first MTJ; and

the second electrical characteristic is based on the second RA product and the second size of the second MTJ; and

rewriting an initial value of a bit stored in the respective MTJ to a desired value of the bit, including;

identifying the respective MTJ that is storing the initial value of the bit as the first MTJ;

adjusting the AC current to a first AC current having a frequency that is tuned to the first write assist frequency corresponding to the first MTJ;

applying the first AC current to the two or more MTJs;

applying the DC current to the two or more MTJs; and

changing the initial value of the bit to the desired value of the bit by changing a magnetic state of the first MTJ without changing the magnetic state of the second MTJ.

5. The method of claim 4, wherein the first electrical characteristic is distinct from the second electrical characteristic.

6. The method of claim 4, wherein the first electrical characteristic corresponds to a baseline resistance that is the same as a baseline resistance corresponding to the second electrical characteristic.

7. The method of claim 4, wherein the memory device further includes a third MTJ having a third magnetic characteristic and a third electrical characteristic, wherein the third magnetic characteristic is distinct from the first magnetic characteristic and the second magnetic characteristic, and wherein the first MTJ, the second MTJ, and the third MTJ are arranged in series with respect to the single terminal of the transistor.