Peripheral component protection in information handling systems

• US 10,809,789 B1
• Filed: 07/17/2019
• Issued: 10/20/2020
• Est. Priority Date: 07/17/2019
• Status: Active Grant

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Lambert, Timothy M., Kennedy, Jeffrey Leighton
• Primary Examiner(s): Abad, Farley
• Assistant Examiner(s): Lewis-Taylor, Dayton
• Application Number:
  US16/514,023
• Time in Patent Office: 461 Days
• Field of Search: None
• CPC Class Codes: G06F 1/3215 Monitoring of peripheral devices
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: G06F 9/4411 Configuring for operating with peripheral devices; Loading of device drivers

Abstract

Logic on the baseboard can be used to provide backfeed protection by determining the condition of the peripheral component before enabling communication over a data cable to the peripheral component. By determining the condition of the peripheral component prior to beginning communications, the baseboard can reduce the likelihood that the baseboard asserts a wire on the data cable before the peripheral component receives power. With such information available to the baseboard, the baseboard avoids supplying a data signal over a wire of the data cable that would cause the destination circuitry of the peripheral component from exceeding its safety specification. When a bias voltage exists on the wire of the data connector corresponding to the peripheral component, the peripheral component is considered powered-on and data can be communicated to the peripheral component. Communications with that peripheral component may be enabled by turning on a clock source to provide a clock signal through the data connector to the peripheral component. The clock signal is then used by the peripheral components to decode data transmitted on the data cable.

Claims

1. A method, comprising:

preventing, by a baseboard of an information handling system configured to be connected to a plurality of peripheral components in parallel, powering on of the information handling system until a determination is made, by the baseboard, that a bias voltage exists on at least one wire of a data connector connecting the information handling system to a peripheral component;

determining, by the baseboard of the information handling system that a bias voltage exists on the at least one wire of the data connector connecting the information handling system to the peripheral component;

enabling, by the information handling system, the peripheral component by activating the data connector when the bias voltage exists on at least one wire of the data connector and allowing the information handling system to power on.

2. The method of claim 1, wherein the peripheral component is powered from a power supply from a different source than the data connector.

3. The method of claim 1, wherein the step of determining that the bias voltage exists comprises:

applying a weak pull-down to the at least one wire; and

determining when a strong pull-up is applied to the at least one wire to override the weak pull-down.

4. The method of claim 3, wherein the step of enabling the peripheral component comprises turning on a clock source for the peripheral component to supply a clock signal through the data connector.

5. The method of claim 1, further comprising determining a configuration of the information handling system, the configuration comprising a listing of a plurality of peripheral components comprising the peripheral component connected to the data connector, and wherein the step of enabling the peripheral component comprises enabling a group of peripheral components that are at least a part of the plurality of peripheral components of the configuration, wherein each of the group of peripheral components being enabled share the data connector.

6. The method of claim 1, wherein preventing powering on of the information handling system comprises preventing completion of a power-on self-test (POST) routine.

7. An apparatus, comprising:

a controller of a baseboard of an information handling system configured to be connected to a plurality of peripheral components in parallel and to perform steps comprising;

preventing powering on of the information handling system until a determination is made, by the controller of the baseboard, that a bias voltage exists on at least one wire of a data connector connecting the information handling system to a peripheral component

determining that a bias voltage exists on the at least one wire of the data connector connecting the information handling system to the peripheral component;

enabling the peripheral component by activating the data connector when the bias voltage exists on at least one wire of the data connector and allowing the information handling system to power on.

8. The apparatus of claim 7, wherein the peripheral component is powered from a power supply from a different source than the data connector.

9. The apparatus of claim 7, wherein the step of determining that the bias voltage exists comprises:

applying a weak pull-down to the at least one wire; and

determining when a strong pull-up is applied to the at least one wire to override the weak pull-down.

10. The apparatus of claim 9, wherein the step of enabling the peripheral component comprises turning on a clock source for the peripheral component to supply a clock signal through the data connector.

11. The apparatus of claim 7, wherein the controller is further configured to perform the step of determining a configuration of the information handling system, the configuration comprising a listing of a plurality of peripheral components comprising the peripheral component connected to the data connector, and wherein the step of enabling the peripheral component comprises enabling a group of peripheral components that are at least a part of the plurality of peripheral components of the configuration, wherein each of the group of peripheral components being enabled share the data connector.

12. The apparatus of claim 7, wherein preventing powering on of the information handling system comprises preventing completion of a power-on self-test (POST) routine.

13. An information handling system, comprising:

a complex programmable logic device (CPLD), of a baseboard of an information handling system configured to be coupled to a plurality of peripheral components in parallel, configured to perform steps comprising;

preventing powering on of the information handling system until a determination is made, by the CPLD of the baseboard, that a bias voltage exists on at least one wire of a data connector connecting the information handling system to a peripheral component;

determining that a bias voltage exists on the at least one wire of the data connector connecting the information handling system to the peripheral component; and

enabling the peripheral component by activating the data connector when the bias voltage exists on at least one wire of the data connector and allowing the information handling system to power on.

14. The information handling system of claim 13, wherein the peripheral component is powered from a power supply from a different source than the data connector.

15. The information handling system of claim 13, wherein the step of determining that the bias voltage exists comprises:

applying a weak pull-down to the at least one wire; and

determining when a strong pull-up is applied to the at least one wire to override the weak pull-down.

16. The information handling system of claim 15, wherein the step of enabling the peripheral component comprises turning on a clock source for the peripheral component to supply a clock signal through the data connector.

17. The information handling system of claim 13, further comprising a baseboard management controller (BMC) configured to perform the step of determining a configuration of the information handling system, the configuration comprising a listing of a plurality of peripheral components comprising the peripheral component connected to the data connector, and wherein the CPLD is configured to perform the step of enabling the peripheral component by enabling a group of peripheral component that are at least a part of the plurality of peripheral component of the configuration under direction of the BMC, wherein each of the group of peripheral components being enabled share the data connector.

18. The information handling system of claim 13, wherein the CPLD comprises a field-programmable gate array (FPGA).

19. The information handling system of claim 13, wherein the CPLD is configured to prevent an input voltage to the peripheral component from exceeding a supply voltage to the peripheral component.

20. The information handling system of claim 13, wherein preventing powering on of the information handling system comprises preventing completion of a power-on self-test (POST) routine.