Semiconductor devices

• US 10,818,727 B2
• Filed: 10/16/2018
• Issued: 10/27/2020
• Est. Priority Date: 04/20/2018
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Son, Myoungsu, Ko, Seung Pil, Lee, Jung Hyuk, Han, Shinhee, Koh, Gwan-Hyeob, Song, Yoonjong
• Primary Examiner(s): Lee, Kyoung
• Assistant Examiner(s): Sylvia, Christina A
• Application Number:
  US16/161,370
• Publication Number:
  US 20190326355A1
• Time in Patent Office: 742 Days
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details

Abstract

A semiconductor device includes a gate structure on a substrate, source and drain contacts respectively on opposite sides of the gate structure and connected to the substrate, a magnetic tunnel junction connected to the drain contact, a first conductive line connected to the source contact, and a second conductive line connected to the first conductive line through a first via contact. The second conductive line is distal to the substrate in relation to the first conductive line. The first and second conductive lines extend in parallel along a first direction. The first and second conductive lines have widths in a second direction intersecting the first direction. The widths of the first and second conductive lines are the same. The first via contact is aligned with the source contact along a third direction perpendicular to a top surface of the substrate.

Claims

1. A semiconductor device, comprising:

a first gate structure and a second gate structure on a substrate, the second gate structure being spaced apart from the first gate structure in a first direction, the first and second gate structures extending in a second direction intersecting the first direction, and the first direction and the second direction being parallel to a top surface of the substrate;

a source contact and a drain contact on opposite sides of the first gate structure, respectively, the source contact and the drain contact each connected to the substrate;

a magnetic tunnel junction connected to the drain contact;

a first conductive line connected to the source contact; and

a second conductive line connected to the first conductive line through a first via contact,

wherein the second conductive line is distal from the substrate in relation to the first conductive line,

wherein the first conductive line and the second conductive line extend in parallel to each other along the first direction and each of the first conductive line and the second conductive line extends over at least some of the first and second gate structures,

wherein each of the first conductive line and the second conductive line has a width in the second direction, the width of the first conductive line and the width of the second conductive line being a same width, and

wherein the first via contact is aligned with the source contact along a third direction perpendicular to the top surface of the substrate.

2. The semiconductor device of claim 1, wherein the first via contact and the second conductive line include a same material.

3. The semiconductor device of claim 1, wherein

each of the first conductive line and the second conductive line has a length in the first direction, and

the length of the first conductive line and the length of the second conductive line is a same length.

4. The semiconductor device of claim 1, further comprising:

a third conductive line connected to the second conductive line through a second via contact,

wherein the third conductive line is distal from the substrate in relation to the second conductive line,

wherein the first conductive line, the second conductive line, and the third conductive line extend in parallel to each other along the first direction, and

wherein the second via contact is aligned with the source contact along the third direction.

5. The semiconductor device of claim 4, wherein, when viewed in plan, the second via contact and the first via contact have a same size and shape.

6. The semiconductor device of claim 4, wherein

the first via contact has a first width in the first direction and a second width in the second direction, and

the second via contact has a third width in the first direction and a fourth width in the second direction,

wherein the first width is substantially the same as the third width, and

wherein the second width is substantially the same as the fourth width.

7. The semiconductor device of claim 4, wherein

the third conductive line has a width in the second direction, and

the width of the third conductive line is the same as the width of the first conductive line in the second direction and the width of the second conductive line in the second direction.

8. The semiconductor device of claim 7, wherein

each of the first conductive line, the second conductive line, and the third conductive line has a length in the first direction, and

the length of the first conductive line in the first direction is the same as both the length of the second conductive line in the first direction and the length of the third conductive line in the first direction.

9. The semiconductor device of claim 4, wherein the second via contact and the third conductive line include a same material.

10. The semiconductor device of claim 4, wherein the first via contact, the second via contact, the first conductive line, the second conductive line, and the third conductive line include a same material.

11. A semiconductor device, comprising:

a substrate including a first active region and a second active region;

a pair of first gate structures extending over the first active region;

a pair of second gate structures extending over the second active region;

a first source contact between the pair of first gate structures, the first source contact connected to the first active region;

a second source contact between the pair of second gate structures, the second source contact connected to the second active region;

a first conductive line extending over the pair of first gate structures and the pair of second gate structures, the first conductive line connected to the first source contact and the second source contact; and

a second conductive line connected to the first conductive line through a plurality of first via contacts,

wherein the second conductive line is distal from the substrate in relation to the first conductive line,

wherein the first conductive line and the second conductive line extend in parallel to each other along a first direction,

wherein one via contact of the plurality of first via contacts is aligned with the first source contact along a direction perpendicular to a top surface of the substrate, and

wherein another via contact of the plurality of first via contacts is aligned with the second source contact along the direction perpendicular to the top surface of the substrate.

12. The semiconductor device of claim 11, wherein the pair of first gate structures and the pair of second gate structures are isolated from direct contact with each other in the first direction and extend in a second direction intersecting the first direction.

13. The semiconductor device of claim 11, wherein the plurality of first via contacts are between the first conductive line and the second conductive line.

14. The semiconductor device of claim 11, wherein the plurality of first via contacts and the second conductive line include a same material.

15. The semiconductor device of claim 11, further comprising:

a third conductive line connected to the second conductive line through a plurality of second via contacts,

wherein the third conductive line is distal from the substrate in relation to the second conductive line,

wherein the first conductive line, the second conductive line, and the third conductive line extend in parallel to each other along the first direction, and

wherein the plurality of second via contacts are correspondingly aligned with the plurality of first via contacts along the direction perpendicular to the top surface of the substrate.

16. The semiconductor device of claim 15, wherein the plurality of second via contacts are between the second conductive line and the third conductive line.

17. The semiconductor device of claim 16, wherein, when viewed in plan, each via contact of the plurality of second via contacts and each via contact of the plurality of first via contacts have a same size and shape.

18. The semiconductor device of claim 16, wherein

each via contact of the plurality of first via contacts has a first width in the first direction and a second width in a second direction perpendicular to the first direction, the first and second directions being parallel to the top surface of the substrate, and each via contact of the plurality of second via contacts has a third width in the first direction and a fourth width in the second direction,

wherein the first width is substantially the same as the third width, and the second width is substantially the same as the fourth width.

19. The semiconductor device of claim 15, wherein the plurality of second via contacts and the third conductive line include a same material.

20. The semiconductor device of claim 15, wherein

one via contact of the plurality of second via contacts is aligned with the first source contact along the direction perpendicular to the top surface of the substrate, and another via contact of the plurality of second via contacts is aligned with the second source contact along the direction perpendicular to the top surface of the substrate.