Vertical transport FET having multiple threshold voltages with zero-thickness variation of work function metal

• US 10,818,756 B2
• Filed: 11/02/2018
• Issued: 10/27/2020
• Est. Priority Date: 11/02/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lee, Choonghyun, Cheng, Kangguo, Li, Juntao, Mochizuki, Shogo
• Primary Examiner(s): Vu, David
• Assistant Examiner(s): Fox, Brandon C
• Application Number:
  US16/178,725
• Publication Number:
  US 20200144378A1
• Time in Patent Office: 725 Days
• Field of Search: 257329, 257347
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A technique relates to a semiconductor device. Fins are formed of varying concentrations of germanium. Gate material is formed on the fins. Source or drain (S/D) regions are adjacent to the fins, and transistor devices include the fins.

Claims

1. A method of forming a semiconductor device, the method comprising:

forming fins of varying concentrations of germanium, one of the fins having a greatest width comprises material having a least concentration of germanium, the fins each comprising a bottom region formed of the material having the least concentration of germanium, wherein the fins comprise varying widths; and

forming gate material on the fins, wherein source or drain (S/D) regions are adjacent to the fins, and wherein transistor devices comprise the fins.

2. The method of claim 1, wherein predefined threshold voltages are defined by differences in the concentrations of germanium, another one of the fins comprising a different concentration of germanium being formed on the bottom region having the material, a further one of the fins comprising a further different concentration of germanium being formed on the bottom region having the material.

3. The method of claim 1, wherein the fins comprise the concentrations of germanium at predefined levels;

and

wherein the fins comprise varying widths as compared to other fins.

4. The method of claim 3, wherein each of the predefined levels is associated with a different threshold voltage for the transistor devices.

5. The method of claim 1, wherein the transistor devices comprise a plurality of threshold voltages.

6. The method of claim 1, wherein the transistor devices comprise different threshold voltages according to the concentrations of germanium.

7. The method of claim 1, wherein threshold voltages of the transistor devices have an inverse relationship to the concentrations of germanium in the fins.

8. The method of claim 1, wherein a greater concentration of germanium is associated with a lower threshold voltage while a lower concentration of germanium is associated with a higher threshold voltage.

9. The method of claim 1, wherein the transistor devices comprise a same thickness of the gate material.

10. The method of claim 1, wherein a work function material of the gate material has a same thickness in the transistor devices.

11. The method of claim 10, wherein the transistor devices comprise multiple threshold voltages.

12. A semiconductor device comprising:

fins comprising varying concentrations of germanium, one of the fins having a greatest width comprises material having a least concentration of germanium, the fins each comprising a bottom region formed of the material having the least concentration of germanium, wherein the fins comprise varying widths; and

gate material formed on the fins, wherein source or drain (S/D) regions are adjacent to the fins, and wherein transistor devices comprise the fins.

13. The semiconductor device of claim 12, wherein predefined threshold voltages are defined by differences in the concentrations of germanium.

14. The semiconductor device of claim 12, wherein the fins comprise the concentrations of germanium at predefined levels;

and

wherein the fins comprise varying widths as compared to other fins.

15. The semiconductor device of claim 14, wherein each of the predefined levels is associated with a different threshold voltage for the transistor devices.

16. The semiconductor device of claim 12, wherein threshold voltages of the transistor devices have an inverse relationship to the concentrations of germanium in the fins.

17. The semiconductor device of claim 12, wherein the transistor devices comprise a same thickness of the gate material.

18. The semiconductor device of claim 12, wherein a work function material of the gate material has a same thickness in the transistor devices.

19. A method of forming a semiconductor device, the method comprising:

forming fins with a first concentration of germanium, one of the fins having a greatest width comprises material having a least concentration of germanium, the fins each comprising a bottom region formed of the material having the least concentration of germanium;

increasing the germanium in at least one of the fins to a second concentration;

increasing the germanium in at least another one of the fins to a third concentration; and

forming gate material on the fins, wherein transistor devices comprise the fins, wherein the transistor devices comprise different threshold voltages defined by the first, second, and third concentrations of the germanium, and wherein the fins comprise varying widths.

20. The method of claim 19, wherein the third concentration of the germanium is greater than the second concentration, and the second concentration is greater than the first concentration.