Memory system architectures using a separate system control path or channel for processing error information

• US 10,824,499 B2
• Filed: 01/08/2018
• Issued: 11/03/2020
• Est. Priority Date: 08/19/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Hu, Chaohong, Zheng, Hongzhong, Kang, Uksong, Ping, Zhan
• Primary Examiner(s): Kudirka, Joseph R
• Application Number:
  US15/865,250
• Publication Number:
  US 20180129553A1
• Time in Patent Office: 1,030 Days
• Field of Search: 714 61, 714 632
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature

Abstract

An embodiment includes a memory module, comprising: a module error interface; and a plurality of memory devices, each memory device coupled to the module error interface, including a data interface and an device error interface, and configured to communicate error information through the device error interface and the module error interface.

Claims

1. A system, comprising:

a memory that stores data, corrects an error in data read from the stored data, and generates error information in response to correcting the error in the data read from the stored data; and

a processor coupled to the memory through a first communication path and a second communication path, the first communication path being part of a main memory path and the second communication path being part of a system control path, the second communication path being separate from the first communication path, the processor;

receiving the data read from the stored data; and

receiving the error information from the memory,

wherein the second communication path comprises an out-of-band communication path with respect to the first communication path.

2. The system of claim 1, wherein the memory is a dynamic random access memory module.

3. The system of claim 1, wherein the second communication path comprises a platform management bus.

4. The system of claim 3, wherein the platform management bus comprises a system management bus (SMBus), an inter-integrated circuit (I²C) bus, an intelligent platform management interface (IPMI) bus, or a Modbus.

5. The system of claim 1, wherein the second communication path is substantially slower than the first communication path.

6. The system of claim 1, wherein the first communication path comprises a first data rate and the second communication path comprises a second data rate, the second data rate being less than or equal to 1/10 of the first data rate.

7. The system of claim 1, wherein the processor receives a poll for error information through the second communication path.

8. The system of claim 1, wherein the memory further pushes error information through the second communication path.

9. The system of claim 1, further comprising:

a controller coupled to the processor through the second communication path.

10. The system of claim 9, wherein the controller is a baseboard management controller.

11. The system of claim 9, wherein the controller:

stores the error information; and

provides the error information to the processor in response to a request received from the processor.

12. A method, comprising:

generating, by an error correction code (ECC) engine within a memory module, error information relating to an error in read data;

receiving at the memory module through a system control channel a command to read the error information, the system control channel being separate from a main memory channel; and

transmitting from the memory module the error information through the system control channel in response to the command.

13. The method of claim 12, wherein the system control channel comprises an out-of-band communication path with respect to the main memory channel.

14. The method of claim 12, wherein the system control channel comprises a platform management bus.

15. A system, comprising:

a memory that corrects an error in data read from the memory, and generates error information in response to correcting the error in the data read from the memory;

a processor coupled to the memory through a main memory channel; and

a system control channel that is separate from the main memory channel, the system control channel being coupled to the memory and the processor;

wherein;

the memory and processor communicate with each other through the main memory channel and the system control channel;

the memory communicates the error information to the processor through the system control channel, and

wherein the system control channel comprises an out-of-band communication path with respect to the main memory channel.

16. The system of claim 15, wherein the processor receives system management information through the system control channel.

17. The system of claim 15, wherein the system control channel comprises a platform management bus.

18. The system of claim 17, wherein the platform management bus comprises a system management bus (SMBus), an inter-integrated circuit (I²C) bus, an intelligent platform management interface (IPMI) bus, or a Modbus.