Semiconductor package having multi-tier bonding wires and components directly mounted on the multi-tier bonding wires

• US 10,847,488 B2
• Filed: 02/12/2018
• Issued: 11/24/2020
• Est. Priority Date: 11/02/2015
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Tsai, Shiann-Tsong
• Primary Examiner(s): Lu, Farun
• Application Number:
  US15/894,874
• Publication Number:
  US 20180166414A1
• Time in Patent Office: 1,016 Days
• CPC Class Codes: H01L 2224/45139 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/45541 Structure
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/4901 Structure
• CPC Class Codes: H01L 2224/8592 Applying permanent coating, e.g. protective coating
• CPC Class Codes: H01L 23/00 Details of semiconductor or other solid state devices H01L25/00 takes precedence ; structural arrangements for testing or measuring during manufacture or treatment, or for reliability measurements H01L22/00; arrangements for connecting or disconnecting semiconductor or solid-state bodies, or methods related thereto H01L24/00; finger print sensors G06V40/12
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/4334 Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

A semiconductor package includes a carrier substrate having a top surface, a semiconductor die mounted on the top surface, a plurality of bonding wires connecting an active surface of the semiconductor die to the top surface of the carrier substrate, an insulating material encapsulating the plurality of bonding wires, a component mounted on the insulating material, and a molding compound covering the top surface of the carrier substrate and encapsulating the semiconductor die, the plurality of bonding wires, the component and the insulating material.

Claims

1. A semiconductor package, comprising:

a carrier substrate having a top surface;

a semiconductor die mounted on the top surface;

a first plurality of bonding wires connecting an active surface of the semiconductor die to the top surface of the carrier substrate;

a second plurality of bonding wires connecting the active surface of the semiconductor die to the top surface of the carrier substrate;

a first insulating material encapsulating the first plurality of bonding wires;

a second insulating material encapsulating the second plurality of bonding wires;

a component mounted on the first insulating material and the second insulating material; and

a molding compound covering the top surface of the carrier substrate and encapsulating the semiconductor die, the first and second plurality of bonding wires, the component and the first and second insulating materials,

wherein the first plurality of bonding wires and the second plurality of bonding wires physically support the component,

wherein the first insulating material coats a top portion of individual bonding wires of the first plurality of bonding wires and is absent from a bottom portion of individual bonding wires of the first plurality of bonding wires, when viewed in cross-sections of individual bonding wires of the first plurality of bonding wires.

2. The semiconductor package according to claim 1, wherein the component comprises a dummy silicon die, a piece of metal, or a heat sink.

3. The semiconductor package according to claim 1, wherein the component is attached to the first insulating material by an adhesive layer.

4. The semiconductor package according to claim 1, wherein the component has a slender shape and its longer axis extends along a diagonal direction of the semiconductor package.

5. The semiconductor package according to claim 1, wherein a longer side of the component is in parallel with a longer side of the semiconductor package.

6. The semiconductor package according to claim 1, wherein the first and second insulating material is disposed in a rectangular, ring shape around the semiconductor die.

7. The semiconductor package according to claim 6, wherein the rectangular, ring-shaped insulating material is continuous.

8. The semiconductor package according to claim 1, wherein the first insulating material and the molding compound have different compositions.

9. The semiconductor package according to claim 1, wherein the carrier substrate comprises a packaging substrate or an interposer substrate.

10. The semiconductor package according to claim 1, further comprising:

a third plurality of bonding wires connecting the component to the carrier substrate,

wherein the molding compound encapsulates the third plurality of bonding wires.

11. The semiconductor package according to claim 10, wherein the component comprises a semiconductor die or a passive device.

12. The semiconductor package according to claim 10, wherein the component is attached to the first insulating material by an adhesive layer.

13. The semiconductor package according to claim 10, wherein the first and second insulating material is disposed in a rectangular, ring shape around the semiconductor die.

14. The semiconductor package according to claim 10, wherein the first insulating material and the molding compound have different compositions.

15. The semiconductor package according to claim 10, further comprising an overhang between an edge of the component and a contact point between the component and the first insulating material.

16. The semiconductor package according to claim 15, wherein the component has a length L, and the overhang has an overhang distance t between the edge of the component and the contact point, and wherein t is greater than ⅓

L and smaller than ½

L.

17. The semiconductor package according to claim 10, further comprising:

a third insulating material encapsulating the third plurality of bonding wires; and

a second component mounted on the third insulating material; and

wherein the molding compound encapsulates the second component and the third plurality of bonding wires.

18. The semiconductor package according to claim 17, wherein the second component comprises a passive device.

19. The semiconductor package according to claim 17 further comprising a fourth plurality of bonding wires connecting the second component to the carrier substrate.