Display device suppressing display failure caused by residual charge

• US 10,854,163 B2
• Filed: 10/04/2019
• Issued: 12/01/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Nishimura, Jun, Watanabe, Takuya
• Primary Examiner(s): Eisen, Alexander
• Assistant Examiner(s): Lam, Nelson
• Application Number:
  US16/592,808
• Publication Number:
  US 20200135136A1
• Time in Patent Office: 424 Days
• Field of Search: 345 87-104
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2330/04 Display protection
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: G09G 3/3696 Generation of voltages supplied to electrode drivers

Abstract

When supply of power has stopped, voltages of GDM signals are set as follows. A clear signal that contributes to removal of charge at floating nodes (an output control node and a stabilization node) in each unit circuit included in a shift register is set to a voltage of ground, and other signals (a gate start pulse signal, gate clock signals, and a reference voltage) are set to a gate-on voltage. To implement such settings, a single power supply system configuration that uses a voltage of only one channel as a scanning line selection voltage is adopted.

Claims

1. A display device comprising:

a display panel including a plurality of scanning lines each connected to a plurality of pixel formation portions, and a scanning line drive circuit configured to selectively drive the plurality of scanning lines;

a voltage generator circuit configured to receive supply of power from an external source, and generate one type of scanning line selection voltage and one type of scanning line non-selection voltage, the scanning line selection voltage being a voltage for bringing the scanning lines into a selected state, and the scanning line non-selection voltage being a voltage for bringing the scanning lines into a non-selected state; and

a drive control circuit configured to control operation of the scanning line drive circuit, using the scanning line selection voltage and the scanning line non-selection voltage generated by the voltage generator circuit, wherein

the scanning line drive circuit includes a shift register configured to perform shift operation based on a plurality of clock signals, the shift register including a plurality of unit circuits provided so as to have one-to-one correspondence with the plurality of scanning lines,

each unit circuit includes;

an output node connected to a corresponding scanning line;

an output control transistor having a control terminal, a first conduction terminal to which one of the plurality of clock signals is provided, and a second conduction terminal connected to the output node;

an output control node connected to the control terminal of the output control transistor; and

a reset transistor having a control terminal to which a clear signal for initializing internal states of the plurality of unit circuits is provided;

a first conduction terminal connected to the output control node; and

a second conduction terminal to which a reference voltage is provided, the reference voltage being outputted from the drive control circuit and serving as a reference for operation of the scanning line drive circuit,

the drive control circuit;

sets a voltage of each of the plurality of clock signals to the scanning line selection voltage and the scanning line non-selection voltage alternately and sets the reference voltage to the scanning line non-selection voltage, at normal times;

sets the voltage of each of the plurality of clock signals and the reference voltage to the scanning line selection voltage and sets a voltage of the clear signal to less than or equal to a voltage of ground without setting the voltage of the clear signal to the scanning line selection voltage, when the supply of power stops,

each unit circuit includes an off control transistor having a control terminal, a first conduction terminal, and a second conduction terminal connected to the output control node, and

the drive control circuit;

sets a voltage provided to the control terminal of the off control transistor and a voltage provided to the first conduction terminal of the off control transistor to the scanning line non-selection voltage at normal times; and

sets the voltage provided to the control terminal of the off control transistor and the voltage provided to the first conduction terminal of the off control transistor to the scanning line selection voltage when the supply of power stops.

2. The display device according to claim 1, wherein an off control signal outputted from the drive control circuit is provided to the control terminal of the off control transistor through a dedicated wiring line.

3. The display device according to claim 2, wherein the off control signal is provided to the first conduction terminal of the off control transistor.

4. The display device according to claim 2, wherein the reference voltage is provided to the first conduction terminal of the off control transistor.

5. A display device comprising:

a display panel including a plurality of scanning lines each connected to a plurality of pixel formation portions, and a scanning line drive circuit configured to selectively drive the plurality of scanning lines;

a voltage generator circuit configured to receive supply of power from an external source, and generate one type of scanning line selection voltage and one type of scanning line non-selection voltage, the scanning line selection voltage being a voltage for bringing the scanning lines into a selected state, and the scanning line non-selection voltage being a voltage for bringing the scanning lines into a non-selected state; and

a drive control circuit configured to control operation of the scanning line drive circuit, using the scanning line selection voltage and the scanning line non-selection voltage generated by the voltage generator circuit, wherein

the scanning line drive circuit includes a shift register configured to perform shift operation based on a plurality of clock signals, the shift register including a plurality of unit circuits provided so as to have one-to-one correspondence with the plurality of scanning lines,

each unit circuit includes;

an output node connected to a corresponding scanning line;

an output control transistor having a control terminal, a first conduction terminal to which one of the plurality of clock signals is provided, and a second conduction terminal connected to the output node;

an output control node connected to the control terminal of the output control transistor; and

a reset transistor having a control terminal to which a clear signal for initializing internal states of the plurality of unit circuits is provided;

a first conduction terminal connected to the output control node; and

a second conduction terminal to which a reference voltage is provided, the reference voltage being outputted from the drive control circuit and serving as a reference for operation of the scanning line drive circuit,

the drive control circuit;

sets a voltage of each of the plurality of clock signals to the scanning line selection voltage and the scanning line non-selection voltage alternately and sets the reference voltage to the scanning line non-selection voltage, at normal times; and

sets the voltage of each of the plurality of clock signals and the reference voltage to the scanning line selection voltage and sets a voltage of the clear signal to less than or equal to a voltage of ground, when the supply of power stops,

the display panel includes a plurality of transistors including the output control transistor and the reset transistor, and

at least some of the plurality of transistors are transistors whose off-leakage current is 1/10 or less than off-leakage current of a thin-film transistor whose channel layer is formed of low-temperature polysilicon.

6. The display device according to claim 5, wherein at least some of the plurality of transistors are thin-film transistors whose channel layers are formed of indium gallium zinc oxide.

7. A display device comprising:

a display panel including a plurality of scanning lines each connected to a plurality of pixel formation portions, and a scanning line drive circuit configured to selectively drive the plurality of scanning lines;

a voltage generator circuit configured to receive supply of power from an external source, and generate one type of scanning line selection voltage and one type of scanning line non-selection voltage, the scanning line selection voltage being a voltage for bringing the scanning lines into a selected state, and the scanning line non-selection voltage being a voltage for bringing the scanning lines into a non-selected state; and

a drive control circuit configured to control operation of the scanning line drive circuit, using the scanning line selection voltage and the scanning line non-selection voltage generated by the voltage generator circuit, wherein

the scanning line drive circuit includes a shift register configured to perform shift operation based on a plurality of clock signals, the shift register including a plurality of unit circuits provided so as to have one-to-one correspondence with the plurality of scanning lines,

each unit circuit includes;

an output node connected to a corresponding scanning line;

an output control transistor having a control terminal, a first conduction terminal to which one of the plurality of clock signals is provided, and a second conduction terminal connected to the output node;

an output control node connected to the control terminal of the output control transistor; and

a reset transistor having a control terminal to which a clear signal for initializing internal states of the plurality of unit circuits is provided;

a first conduction terminal connected to the output control node; and

a second conduction terminal to which a reference voltage is provided, the reference voltage being outputted from the drive control circuit and serving as a reference for operation of the scanning line drive circuit,

the drive control circuit;

sets a voltage of each of the plurality of clock signals to the scanning line selection voltage and the scanning line non-selection voltage alternately and sets the reference voltage to the scanning line non-selection voltage, at normal times; and

sets the voltage of each of the plurality of clock signals and the reference voltage to the scanning line selection voltage and sets a voltage of the clear signal to less than or equal to a voltage of ground, when the supply of power stops,

each unit circuit includes an off control transistor having a control terminal, a first conduction terminal, and a second conduction terminal connected to the output control node, and

the drive control circuit;

sets a voltage provided to the control terminal of the off control transistor and a voltage provided to the first conduction terminal of the off control transistor to the scanning line non-selection voltage at normal times; and

sets the voltage provided to the control terminal of the off control transistor and the voltage provided to the first conduction terminal of the off control transistor to the scanning line selection voltage when the supply of power stops.

8. The display device according to claim 7, wherein an off control signal outputted from the drive control circuit is provided to the control terminal of the off control transistor through a dedicated wiring line.

9. The display device according to claim 7, wherein the off control signal is provided to the first conduction terminal of the off control transistor.

10. The display device according to claim 7, wherein the reference voltage is provided to the first conduction terminal of the off control transistor.