Configuring different via sizes for bridging risk reduction and performance improvement

• US 10,854,518 B2
• Filed: 02/07/2019
• Issued: 12/01/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liaw, Jhon Jhy
• Primary Examiner(s): Garces, Nelson
• Application Number:
  US16/269,747
• Publication Number:
  US 20200135569A1
• Time in Patent Office: 663 Days
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A first gate structure, a second gate structure, and a third gate structure each extend in a first direction. A first gate via is disposed on the first gate structure. The first gate via has a first size. A second gate via is disposed on the second gate structure. The second gate via has a second size that is greater than the first size. A third gate via is disposed on the third gate structure. The third gate via has a third size that is less than the second size but greater than the first size. A first source contact is disposed adjacent to a first side of the first gate via. A first drain contact is disposed adjacent to a second side of the first gate via opposite the first side. A second drain contact is disposed adjacent to a first side of the third gate via.

Claims

1. A semiconductor device, comprising:

a first gate structure, a second gate structure, and a third gate structure that each extend in a first direction;

a first gate via disposed on the first gate structure, the first gate via having a first size;

a second gate via disposed on the second gate structure, the second gate via having a second size that is greater than the first size;

a third gate via disposed on the third gate structure, the third gate via having a third size that is less than the second size but greater than the first size;

a first source contact disposed adjacent to a first side of the first gate via;

a first drain contact disposed adjacent to a second side of the first gate via opposite the first side; and

a second drain contact is disposed adjacent to a first side of the third gate via;

wherein;

the first gate structure, the first gate via, the second gate structure, and the second gate via are components of a first circuit cell;

the third gate structure and the third gate via are components of a second circuit cell; and

the first circuit cell and the second circuit cell are different types of circuit cells.

2. The semiconductor device of claim 1, wherein:

no source contact or drain contact is disposed adjacent to a first side or a second side of the second gate via; and

no source contact or drain contact is disposed adjacent to a second side of the third gate via that is opposite the first side.

3. The semiconductor device of claim 1, wherein:

the semiconductor device further includes a plurality of fin structures that each extend in a second direction different from the first direction;

the first, second, and third gate structures each wrap around the fin structures;

the first gate via is disposed over one of the fin structures; and

the second gate via and the third gate via are not disposed over any of the fin structures.

4. The semiconductor device of claim 1, wherein the third gate via is shifted with respect to the third gate structure in a direction away from the second drain contact.

5. The semiconductor device of claim 1, wherein the first source contact has a larger dimension in the first direction than the first drain contact.

6. The semiconductor device of claim 1, wherein the semiconductor device further includes:

a plurality of first metal lines and second metal lines of an interconnect structure, wherein the first metal lines and second metal lines each extend in a second direction different from the first direction;

a plurality of drain contacts that include the first drain contact and the second drain contact, wherein the drain contacts each extend in the first direction;

a plurality of source contacts that include the first source contact, wherein the sources contacts each extend in the first direction;

a plurality of drain vias that are disposed between, and electrically coupled to, the drain contacts and the first metal lines; and

a plurality of source vias that are disposed between, and electrically coupled to, the source contacts and the second metal lines, wherein a size of each of the source vias is substantially greater than a size of each of the drain vias.

7. The semiconductor device of claim 6, wherein:

each of the drain vias has a circular or elliptical top view profile; and

each of the source vias has an elongated top view profile, the source vias each being elongated in the second direction and each being electrically coupled to multiple ones of the source contacts.

8. The semiconductor device of claim 6, wherein:

each of the drain vias has a first circular or first elliptical top view profile;

each of the source vias has a second circular or second elliptical top view profile; and

a dimension of each of the source vias in a top view is at least 1.5 times a dimension of each of the drain vias in the second direction.

9. A semiconductor device, comprising:

a first gate structure, a second gate structure, and a third gate structure that each extend in a first direction;

a plurality of fin structures that each extend in a second direction perpendicular to the first direction, wherein the fin structures are each wrapped around by the first gate structure, the second gate structure, and third gate structure;

a first gate via disposed on the first gate structure, the first gate via having a first dimension, wherein the first gate via overlap with one of the fin structures in a top view;

a second gate via disposed on the second gate structure, the second gate via having a second dimension that is greater than the first dimension, wherein the second gate via does not overlap with any of the fin structures in the top view; and

a third gate via disposed on the third gate structure, the third gate via having a third dimension that is less than the second dimension but greater than the first dimension, wherein the third gate via does not overlap with any of the fin structures in the top view; and

a plurality of source/drain contacts that each extend in the first direction;

wherein;

both a first side and a second side of the first gate via have source/drain contacts located adjacent thereto, wherein the first side and the second side are opposite one another in the second direction;

neither a first side nor a second side of the second gate via has source/drain contacts located adjacent thereto; and

a first side but not a second side of the third gate via has one of the source/drain contacts located adjacent thereto.

10. The semiconductor device of claim 9, wherein a center of the third gate via is offset with respect to a center of the third gate structure in the second direction away from the one of the source/drain contacts that is located adjacent thereto.

11. The semiconductor device of claim 9, wherein:

a first subset of the source/drain contacts include source contacts;

a second subset of the source/drain contacts include drain contacts; and

the source contacts and the drain contacts have different dimensions in the first direction.

12. The semiconductor device of claim 9, wherein the semiconductor device further includes a drain via and a source via, wherein the source via has a larger area in the top view than the drain via.

13. The semiconductor device of claim 12, wherein:

the drain via has a circular or elliptical top view profile; and

the source via has a rectangular top view profile that is elongated in the second direction.

20. The semiconductor device of claim 9, wherein:

the first gate structure, the first gate via, the second gate structure, and the second gate via are components of a first circuit cell;

the third gate structure and the third gate via are components of a second circuit cell; and

the first circuit cell and the second circuit cell are different types of circuit cells.

14. A semiconductor device, comprising:

a first gate structure, a second gate structure, and a third gate structure that each extend in an elongated manner in a first direction;

a plurality of fin structures that each extend in an elongated manner in a second direction that is different from the first direction, wherein the fin structures each intersect with one or more of the first, second, and third gate structures in a top view;

a first gate via disposed over the first gate structure and over one of the fin structures, the first gate via having a first size;

a second gate via disposed over the second gate structure but not over any of the fin structures, the second gate via having a second size that is greater than the first size;

a third gate via disposed over the third gate structure but not over any of the fin structures, the third gate via having a third size that is less than the second size but greater than the first size;

a first source contact disposed adjacent to a first side of the first gate via;

a first drain contact disposed adjacent to a second side of the first gate via opposite the first side, wherein the first drain contact is smaller than the first source contact in the first direction; and

a second drain contact is disposed adjacent to a first side of the third gate via.

15. The semiconductor device of claim 14, wherein:

no source contact or drain contact is disposed adjacent to a first side or a second side of the second gate via in the second direction; and

no source contact or drain contact is disposed adjacent to a second side of the third gate via that is opposite the first side in the second direction.

16. The semiconductor device of claim 14, wherein the third gate via is at least partially misaligned with the third gate structure.

17. The semiconductor device of claim 14, wherein:

the semiconductor device includes a first circuit cell and a second circuit cell that is a different type of circuit cell than the first circuit cell;

the first circuit cell includes the first gate, the first gate via, the second gate, and the second gate via; and

the second circuit cell includes the third gate and the third gate via.

18. The semiconductor device of claim 14, wherein the semiconductor device further includes:

a plurality of first metal lines and second metal lines of an interconnect structure, wherein the first metal lines and second metal lines each extend in the second direction;

a plurality of drain contacts that include the first drain contact and the second drain contact, wherein the drain contacts each extend in the first direction;

a plurality of source contacts that include the first source contact, wherein the sources contacts each extend in the first direction;

a plurality of drain vias that are disposed between, and electrically coupled to, the drain contacts and the first metal lines; and

a plurality of source vias that are disposed between, and electrically coupled to, the source contacts and the second metal lines, wherein a size of each of the source vias is substantially greater than a size of each of the drain vias.

19. The semiconductor device of claim 18, wherein:

each of the drain vias has a circular or elliptical top view profile; and

each of the source vias has one of;

an elongated top view profile, the source vias each being elongated in the second direction and each being electrically coupled to multiple ones of the source contacts;

or

a second circular top view profile or a second elliptical top view profile.