Packages with Si-substrate-free interposer and method forming same

• US 10,854,568 B2
• Filed: 07/12/2017
• Issued: 12/01/2020
• Est. Priority Date: 04/07/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Ming-Fa, Yu, Chen-Hua
• Primary Examiner(s): Mandala, Michelle
• Assistant Examiner(s): Klein, Jordan M
• Application Number:
  US15/647,704
• Publication Number:
  US 20180294241A1
• Time in Patent Office: 1,238 Days
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68318 Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/0613 Square or rectangular array
• CPC Class Codes: H01L 2224/08225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/09181 On opposite sides of the body
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/29186 with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/33181 On opposite sides of the body
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/80004 being a removable or sacrificial coating
• CPC Class Codes: H01L 2224/80006 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/80447 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/80895 : between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/80896 : between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/82005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/83002 : being a removable or sacrificial coating
• CPC Class Codes: H01L 2224/83005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/83896 : between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/5381 : Crossover interconnections, e.g. bridge stepovers
• CPC Class Codes: H01L 23/5383 : Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5386 : Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/09 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/05442 : SiO2
• CPC Class Codes: H01L 2924/07025 : Polyimide
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip

Abstract

A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, etching the plurality of dielectric layers to form an opening, filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers, forming an insulation layer over the through-dielectric via and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, and bonding a device to the insulation layer and a portion of the plurality of bond pads through hybrid bonding.

Claims

1. A method comprising:

forming a plurality of dielectric layers;

forming a plurality of redistribution lines in the plurality of dielectric layers;

etching the plurality of dielectric layers to form an opening, wherein the opening extends from a top surface of a top dielectric layer of the plurality of dielectric layers to a bottom surface of a bottom dielectric layer of the plurality of dielectric layers;

filling the opening to form a through-dielectric via penetrating through all of the plurality of dielectric layers;

forming an insulation layer over the through-dielectric via and the plurality of dielectric layers;

forming a plurality of bond pads in the insulation layer;

bonding a first device to the insulation layer and a first portion of the plurality of bond pads;

forming an oxide layer overlying and contacting a semiconductor substrate of the first device;

forming a bond pad extending into the oxide layer; and

bonding a bulk wafer to the oxide layer and the bond pad through hybrid bonding, wherein the bulk wafer comprises a bottom surface in physical contact with the oxide layer and the bond pad, and wherein an entire of the bulk wafer from the bottom surface to a top surface of the bulk wafer is free from active devices and passive devices therein.

2. The method of claim 1 further comprising bonding a second device to the insulation layer and a second portion of the plurality of bond pads through hybrid bonding, wherein the plurality of redistribution lines connects the first device to the second device.

3. The method of claim 1, wherein the forming the plurality of redistribution lines comprises damascene processes, and the opening is formed after the damascene processes are performed.

4. The method of claim 1, wherein both of the opening and the through-dielectric via are formed after the plurality of redistribution lines are formed.

5. The method of claim 1, wherein the bond pad extends into the semiconductor substrate of the first device.

6. The method of claim 1, wherein the bond pad contacts, without extending into, the semiconductor substrate of the first device.

7. The method of claim 1, wherein the bulk wafer comprises:

a bulk substrate; and

an additional oxide layer and an additional bond pad in the additional oxide layer, wherein the additional oxide layer and the additional bond pad are in physical contact with the bulk substrate, and are physically bonded to the oxide layer and the bond pad, respectively.

8. The method of claim 7, wherein the bulk substrate comprises silicon.

9. The method of claim 7, wherein the bulk substrate comprises a metal.

20. The method of claim 1, wherein at least a portion of the through-dielectric via is formed at a same level as a portion of one of the plurality of redistribution lines.

10. A method comprising:

forming a plurality of dielectric layers;

forming a plurality of redistribution lines in the plurality of dielectric layers;

forming a first through-dielectric via and a second through-dielectric via penetrating through the plurality of dielectric layers;

forming an insulation layer over the plurality of dielectric layers;

forming a plurality of bond pads in the insulation layer and electrically coupling to the first and the second through-dielectric vias and the plurality of redistribution lines;

bonding a first device and a second device to the insulation layer and portions of the plurality of bond pads, wherein the first device and the second device are electrically interconnected through at least one of the plurality of redistribution lines;

thinning the first device and the second device;

filling a gap-filling material into a gap between the first device and the second device;

forming an additional dielectric layer over the first device and the second device; and

bonding a bulk wafer to the additional dielectric layer, wherein the bulk wafer is free from active device and passive devices therein.

11. The method of claim 10, wherein the first through-dielectric via is continuous, and no interface is formed between portions of the first through-dielectric via that are located in neighboring ones of the plurality of dielectric layers.

12. The method of claim 10 further comprising:

forming a polymer layer over a carrier;

forming a passivation layer over the polymer layer, wherein the plurality of dielectric layers is formed over the passivation layer;

forming additional redistribution lines in the polymer layer and the passivation layer; and

detaching the carrier from the polymer layer.

13. The method of claim 10, wherein the plurality of dielectric layers is formed over a carrier, and the method further comprises:

de-bonding the plurality of dielectric layers from the carrier to reveal a bottom dielectric layer in the plurality of dielectric layers; and

forming solder regions to penetrate through the bottom dielectric layer.

14. The method of claim 10, wherein the forming the first through-dielectric via and the second through-dielectric via comprises:

etching the plurality of dielectric layers to form a first opening and a second opening; and

filling the first opening and the second opening with a conductive material.

15. A package comprising:

a plurality of dielectric layers;

a plurality of redistribution lines in the plurality of dielectric layers;

a through-dielectric via penetrating through the plurality of dielectric layers, wherein the through-dielectric via comprises a substantially straight edge extending from a top surface of a top dielectric layer of the plurality of dielectric layers to a bottom surface of a bottom dielectric layer of the plurality of dielectric layers;

a plurality of bond pads over and connected to the through-dielectric via and the plurality of redistribution lines;

a first insulation layer, with the plurality of bond pads located in the first insulation layer;

a first device bonded to the first insulation layer and a first portion of the plurality of bond pads, wherein the first device comprises;

surface metal features bonded to the plurality of bond pads; and

a surface dielectric layer bonded to the first insulation layer; and

a second device bonded to the first insulation layer and a second portion of the plurality of bond pads through hybrid bonding, wherein the first device and the second device are electrically coupled to each other through the plurality of redistribution lines.

16. The package of claim 15 further comprising:

a bond pad physically contacting a semiconductor substrate of the first device;

a second insulation layer, with the bond pad having at least a portion in the second insulation layer; and

a bulk substrate bonded to the second insulation layer and the bond pad, wherein the bulk substrate is free from active devices and passive devices therein.

17. The package of claim 16, wherein the bulk substrate is formed of silicon.

18. The package of claim 16, wherein the bond pad further extends into the semiconductor substrate of the first device.

19. The package of claim 16, wherein the bond pad forms a grid, wherein the grid comprises a first plurality of strips extending in a first direction, and a second plurality of strips extending in a second direction, and wherein the first plurality of strips join the second plurality of strips to form the grid.