High power gallium nitride electronics using miscut substrates
First Claim
Patent Images
1. A field effect transistor comprising:
- a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <
0001>
direction towards the <
1100>
direction by an angle ranging between −
0.3° and
−
0.6° and
towards the <
1120>
direction by an angle ranging between −
0.1° and
−
0.2°
;
a first epitaxial layer coupled to the III-V substrate;
a second epitaxial layer coupled to the first epitaxial layer;
one or more recessed regions extending into the second epitaxial layer, wherein each of the one or more recessed regions defines a sidewall surface in the second epitaxial layer and a lateral surface, wherein a doped region extends into the sidewall surface and the lateral surface;
a drain contact in electrical contact with the III-V substrate;
a source contact in electrical contact with the second epitaxial layer; and
a gate contact in electrical contact with the doped region.
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Accused Products
Abstract
A method of fabricating an electronic device includes providing a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15° and 0.65°. The method also includes growing a first III-V epitaxial layer coupled to the III-V substrate and growing a second III-V epitaxial layer coupled to the first III-V epitaxial layer. The method further includes forming a first contact in electrical contact with the III-V substrate and forming a second contact in electrical contact with the second III-V epitaxial layer.
12 Citations
18 Claims
-
1. A field effect transistor comprising:
-
a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <
0001>
direction towards the <
11 00>
direction by an angle ranging between −
0.3° and
−
0.6° and
towards the <
112 0>
direction by an angle ranging between −
0.1° and
−
0.2°
;a first epitaxial layer coupled to the III-V substrate; a second epitaxial layer coupled to the first epitaxial layer; one or more recessed regions extending into the second epitaxial layer, wherein each of the one or more recessed regions defines a sidewall surface in the second epitaxial layer and a lateral surface, wherein a doped region extends into the sidewall surface and the lateral surface; a drain contact in electrical contact with the III-V substrate; a source contact in electrical contact with the second epitaxial layer; and a gate contact in electrical contact with the doped region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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Specification