Positive logic switch with selectable DC blocking circuit

  • US 10,862,473 B2
  • Filed: 11/13/2019
  • Issued: 12/08/2020
  • Est. Priority Date: 03/28/2018
  • Status: Active Grant
First Claim
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1. A stack of FET switches, at least one FET switch configured so as to require a relative negative VGs to effectively turn the FET switch OFF but to not require a negative voltage source, series-coupled on a first end to a first end-cap FET that effectively turns OFF when the VGs of such end-cap FET is essentially at zero volts, wherein the first end-cap FET is configured to selectably provide either a capacitive DC blocking function or a resistive signal path.

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