Read circuit for magnetic tunnel junction (MTJ) memory

• US 10,867,652 B2
• Filed: 07/03/2019
• Issued: 12/15/2020
• Est. Priority Date: 10/29/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Gupta, Gaurav, Wu, Zhiqiang
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US16/502,430
• Publication Number:
  US 20200135252A1
• Time in Patent Office: 531 Days
• Field of Search: 365158
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1693 Timing circuits or methods
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details
• CPC Class Codes: H10N 50/85 Magnetic active materials

Abstract

In some embodiments, the present application provides a memory device. The memory device includes a first current mirror transistor, a first pull-up read-enable transistor, an MTJ memory cell, a first pull-down read-enable transistor, and a first non-linear resistance device. The MTJ memory cell includes an MTJ memory element and a first access transistor. The first non-linear resistance device is coupled in series and between the first pull-up read-enable transistor and the first current mirror transistor. The first non-linear resistance device is configured to provide a first resistance when conducting a first current and a second resistance greater than the first resistance when conducting a second current smaller than the first current.

Claims

1. A memory device, comprising:

a magnetic tunnel junction (MTJ) current path, the MTJ current path comprising;

a first current mirror transistor;

a first pull-up read-enable transistor connected in series with the first current mirror transistor;

an MTJ memory cell connected in series with the first pull-up read-enable transistor and including an MTJ memory element and a first access transistor;

a first pull-down read-enable transistor connected in series with the MTJ memory cell; and

a first non-linear resistance device connected in series and between the first pull-up read-enable transistor and the first current mirror transistor, wherein the first non-linear resistance device is configured to provide a first resistance when conducting a first current and a second resistance greater than the first resistance when conducting a second current smaller than the first current.

2. The memory device of claim 1, wherein the first non-linear resistance device is an S-type negative resistor or an equivalent sub-circuit.

3. The memory device of claim 1, wherein the first non-linear resistance device is a silicon control rectifier (SCR) or a triac.

4. The memory device of claim 1, further comprising:

a reference current path in parallel with the MTJ current path, the reference current path comprising;

a second current mirror transistor;

a second pull-up read-enable transistor in series with the second current mirror transistor;

a reference memory cell including a reference MTJ memory element and a second access transistor;

a second pull-down read-enable transistor; and

a second non-linear resistance device coupled between the second pull-up read-enable transistor and the second current mirror transistor.

5. The memory device of claim 4, further comprising:

a sense amplifier having a first input terminal and a second input terminal that are configured to receive a differential input signal, the first input terminal coupled to a first node on the MTJ current path and the second input terminal coupled to a second node on the reference current path.

6. The memory device of claim 5, wherein the first node of the MTJ current path to which the first input terminal of the sense amplifier is coupled is located between the first current mirror transistor and the first pull-up read-enable transistor.

7. The memory device of claim 5, wherein the second node of the MTJ current path to which the second input terminal of the sense amplifier is coupled is located between the second current mirror transistor and the second pull-up read-enable transistor.

8. The memory device of claim 1, wherein the MTJ memory cell is configured to switch between a first data state and a second data state, the first data state having a first resistance and the second data state having a second resistance greater than the first resistance.

9. The memory device of claim 1,

wherein a source-line is coupled between the MTJ memory element and the first pull-down read-enable transistor;

and

wherein a bit-line is coupled between the first pull-up read-enable transistor and the MTJ memory cell.

10. The memory device of claim 9, wherein the MTJ memory element comprises:

a ferromagnetic free layer connected to the bit-line;

a ferromagnetic reference layer connected to the source-line; and

a non-magnetic barrier layer disposed between and separating the ferromagnetic reference layer and the ferromagnetic free layer.

11. A memory device, comprising:

a magnetic tunnel junction (MTJ) current path comprising a first current mirror transistor, a first pull-up read-enable transistor, an MTJ memory cell, and a first pull-down read-enable transistor, wherein a source-line is coupled between the MTJ memory cell and the first pull-down read-enable transistor; and

wherein a bit-line is coupled between the first pull-up read-enable transistor and the MTJ memory cell;

a reference current path in parallel with the MTJ current path, the reference current path comprising a second current mirror transistor, a second pull-up read-enable transistor, a reference memory cell, and a second pull-down read-enable transistor, wherein a reference bit-line is coupled between the second pull-up read-enable transistor and the reference memory cell, and wherein a reference source-line is coupled between the reference memory cell and the second pull-down read-enable transistor; and

a first non-linear resistance device coupled in the MTJ current path between the first pull-up read-enable transistor and the first current mirror transistor, wherein the first non-linear resistance device is configured to increase an effective tunnel magnetoresistance (TMR) of the MTJ current path.

12. The memory device of claim 11, wherein the first non-linear resistance device comprises an S-type negative resistor.

13. The memory device of claim 11, wherein the reference current path further comprises a second non-linear resistance device coupled between the second pull-up read-enable transistor and the second current mirror transistor.

14. The memory device of claim 11, wherein the MTJ memory cell is configured to switch between a first data state and a second data state, the first data state having a first resistance (R_P) and the second data state having a second resistance (R_AP) greater than the first resistance;

wherein the first non-linear resistance device is configured to provide a first resistance(r_nlr) when the first data state is read and a second resistance (R_nlr) greater than the first resistance (r_nlr) when the second data state is read.

15. The memory device of claim 14,

wherein the reference memory cell having a reference resistance greater than a sum of the first resistance (R_P) of the MTJ memory cell and the first resistance (r_nlr) of the first non-linear resistance device;

and

wherein the reference memory cell having a reference resistance smaller than a sum of the second resistance (R_AP) of the MTJ memory cell and the second resistance (R_nlr) of the first non-linear resistance device.

16. The memory device of claim 11, further comprising:

a sense amplifier having a first input terminal and a second input terminal that are configured to receive a differential input signal, the first input terminal coupled to the MTJ memory cell and the second input terminal coupled to the reference memory cell.

17. A method for reading from an MTJ memory device, comprising:

providing a magnetic tunnel junction (MTJ) current path and a reference current path in parallel with the MTJ current path, wherein the MTJ current path comprises an MTJ memory cell connected in series with a first non-linear resistance device;

providing a reading voltage (V_READ) to generate an MTJ current (I_MTJ) through the MTJ current path and to generate a reference current (I_REF) through the reference current path; and

comparing the reference current I_REF and the MTJ current I_MTJ with one another to determine a status of the MTJ memory cell between a first data state having a first resistance and a second data state having a second resistance, the first data state differing from the second data state.

18. The method of claim 17, further comprising:

sensing a differential current between the MTJ current path and the reference current path, and providing a voltage detection signal based on the sensed differential current; and

buffering the voltage detection signal to output a digital signal indicating a data state of the MTJ memory device.

19. The method of claim 17, wherein the first non-linear resistance device provides a first resistance(r_nlr) when the MTJ memory device is in a low-resistance state and a second resistance (R_nlr) greater than the first resistance (r_nlr) when the MTJ memory device is in a low-resistance state.

20. The method of claim 17, wherein operating points of the first non-linear resistance device for the first data state and the second data state are chosen to be different regions on either side of a negative region of an IV characteristic curve of the first non-linear resistance device.