Semiconductor device applying an oxide semiconductor

• US 10,868,046 B2
• Filed: 02/15/2019
• Issued: 12/15/2020
• Est. Priority Date: 11/06/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun, Miyake, Hiroyuki
• Primary Examiner(s): Bradley, Stephen M
• Application Number:
  US16/277,026
• Publication Number:
  US 20190181160A1
• Time in Patent Office: 669 Days
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1229 with different crystal properties within a device or between different devices
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/247 Amorphous materials
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H10K 59/1213 : the pixel elements being TFTs

Abstract

An object of an embodiment of the present invention is to manufacture a semiconductor device with high display quality and high reliability, which includes a pixel portion and a driver circuit portion capable of high-speed operation over one substrate, using transistors having favorable electric characteristics and high reliability as switching elements. Two kinds of transistors, in each of which an oxide semiconductor layer including a crystalline region on one surface side is used as an active layer, are formed in a driver circuit portion and a pixel portion. Electric characteristics of the transistors can be selected by choosing the position of the gate electrode layer which determines the position of the channel. Thus, a semiconductor device including a driver circuit portion capable of high-speed operation and a pixel portion over one substrate can be manufactured.

Claims

1. A semiconductor device comprising:

a first transistor and a second transistor;

the first transistor comprising;

a first conductive layer over a substrate;

a first insulating layer over the first conductive layer;

a first oxide semiconductor layer over the first insulating layer;

a first source electrode layer and a first drain electrode layer each of which has a region overlapping with part of the first oxide semiconductor layer; and

a second insulating layer having a region in contact with part of the first oxide semiconductor layer;

the second transistor comprising;

the first insulating layer over the substrate;

a second oxide semiconductor layer over the first insulating layer;

a second source electrode layer and a second drain electrode layer each of which has a region overlapping with part of the second oxide semiconductor layer; and

the second insulating layer having a region in contact with part of the second oxide semiconductor layer; and

a second conductive layer over the second insulating layer,

wherein a surface portion of the first oxide semiconductor layer comprises a crystal region,

wherein the crystal region comprises a first region in contact with the first source electrode layer, a second region in contact with the first drain electrode layer, and a third region, which is sandwiched between the first region and the second region and overlaps with the first conductive layer, in contact with the second insulating layer, and

wherein the crystal region is c-axis-aligned.

2. The semiconductor device according to claim 1, wherein the first oxide semiconductor layer comprises indium.

3. The semiconductor device according to claim 2, wherein the first oxide semiconductor layer further comprises gallium and zinc.

4. The semiconductor device according to claim 1, wherein the crystal region contains a crystal having a particle size greater than or equal to 1 nm and less than or equal to 20 nm.

5. The semiconductor device according to claim 1, wherein each of the first conductive layer, the first source electrode layer, the first drain electrode layer, the second source electrode layer, and the second drain electrode layer is a conductive layer having a light transmitting property.

6. The semiconductor device according to claim 1, wherein the first source electrode layer, the second source electrode layer, the first drain electrode layer, and the second drain electrode layer comprise titanium.

7. The semiconductor device according to claim 1, wherein the first source electrode layer, the second source electrode layer, the first drain electrode layer, and the second drain electrode layer comprise an element selected from chromium, tantalum, molybdenum, tungsten, and a combination thereof.

8. The semiconductor device according to claim 1,

wherein the first oxide semiconductor layer comprises a channel formation region, and

wherein a donor concentration of the channel formation region is lower than or equal to 1×

10¹⁸/cm³.

9. A semiconductor device comprising:

a first transistor and a second transistor;

the first transistor comprising;

a first conductive layer over a substrate;

a first insulating layer over the first conductive layer;

a first oxide semiconductor layer over the first insulating layer;

a first source electrode layer and a first drain electrode layer each of which has a region overlapping with part of the first oxide semiconductor layer; and

a second insulating layer having a region in contact with part of the first oxide semiconductor layer;

the second transistor comprising;

the first insulating layer over the substrate;

a second oxide semiconductor layer over the first insulating layer;

a second source electrode layer and a second drain electrode layer each of which has a region overlapping with part of the second oxide semiconductor layer; and

the second insulating layer having a region in contact with part of the second oxide semiconductor layer; and

a second conductive layer over the second insulating layer,

wherein a surface portion of the first oxide semiconductor layer comprises a first crystal region,

wherein the first crystal region comprises a first region in contact with the first source electrode layer, a second region in contact with the first drain electrode layer, and a third region, which is sandwiched between the first region and the second region and overlaps with the first conductive layer, in contact with the second insulating layer,

wherein a surface portion of the second oxide semiconductor layer comprises a second crystal region,

wherein the second crystal region comprises a fourth region in contact with the second source electrode layer, a fifth region in contact with the second drain electrode layer, and a sixth region, which is sandwiched between the fourth region and the fifth region and overlaps with the second conductive layer, in contact with the second insulating layer, and

wherein each of the first crystal region and the second crystal region is c-axis-aligned.

10. The semiconductor device according to claim 9, wherein the first oxide semiconductor layer comprises indium.

11. The semiconductor device according to claim 10, wherein the first oxide semiconductor layer further comprises gallium and zinc.

12. The semiconductor device according to claim 9, wherein each of the first and the second crystal region contains a crystal having a particle size greater than or equal to 1 nm and less than or equal to 20 nm.

13. The semiconductor device according to claim 9, wherein each of the first conductive layer, the first source electrode layer, the first drain electrode layer, the second source electrode layer, and the second drain electrode layer is a conductive layer having a light transmitting property.

14. The semiconductor device according to claim 9, wherein the first source electrode layer, the second source electrode layer, the first drain electrode layer, and the second drain electrode layer comprise titanium.

15. The semiconductor device according to claim 9, wherein the first source electrode layer, the second source electrode layer, the first drain electrode layer, and the second drain electrode layer comprise an element selected from chromium, tantalum, molybdenum, tungsten, and a combination thereof.

16. The semiconductor device according to claim 9,

wherein the first oxide semiconductor layer comprises a channel formation region, and

wherein a donor concentration of the channel formation region is lower than or equal to 1×

10¹⁸/cm³.

17. A display device comprising:

a first transistor and a second transistor each of which is over a substrate,

the first transistor comprising;

a first conductive layer;

a first oxide semiconductor layer over the first conductive layer;

a first source electrode layer and a first drain electrode layer each of which comprises a region overlapping with the first oxide semiconductor layer; and

a second conductive layer over the first oxide semiconductor layer,

the second transistor comprising;

a second oxide semiconductor layer;

a second source electrode layer and a second drain electrode layer each of which comprises a region overlapping with the second oxide semiconductor layer; and

a third conductive layer over the second oxide semiconductor layer,

wherein the first oxide semiconductor layer comprises a region including a nanocrystal,

wherein the first oxide semiconductor layer comprises a region overlapping with the first conductive layer and the second conductive layer between the first source electrode layer and the first drain electrode layer, and

wherein the second oxide semiconductor layer comprises a region overlapping with the third conductive layer between the second source electrode layer and the second drain electrode layer.

18. The display device according to claim 17, wherein the nanocrystal has a particle size greater than or equal to 1 nm and less than or equal to 20 nm.

19. The display device according to claim 17, wherein an end portion of the first oxide semiconductor layer has a tapered shape.

20. The display device according to claim 17, wherein the first conductive layer contains an element selected from Al, Cr, Ta, Ti, Mo, and W.

21. The display device according to claim 17, wherein the first source electrode layer and the first drain electrode layer contain an element selected from Al, Cu, Cr, Ta, Ti, Mo, and W.

22. The display device according to claim 17, wherein the first oxide semiconductor layer has a thickness greater than or equal to 5 nm and less than or equal to 200 nm.

23. The display device according to claim 17,

wherein the first oxide semiconductor layer comprises a first region including a first crystal and a second region including a second crystal, and

wherein a crystal state of the first region is different from the crystal state of the second region.

24. The display device according to claim 17,

wherein the first oxide semiconductor layer comprises a region overlapping with the first conductive layer with a first insulating layer provided therebetween, and

wherein the first insulating layer comprises silicon oxide.

25. The display device according to claim 17,

wherein the first oxide semiconductor layer comprises a region overlapping with the second conductive layer with a second insulating layer provided therebetween, and

wherein the second insulating layer comprises silicon oxide.

26. A display device comprising:

a first transistor and a second transistor each of which is over a substrate,

the first transistor comprising;

a first conductive layer;

a first oxide semiconductor layer over the first conductive layer;

a first source electrode layer and a first drain electrode layer each of which comprises a region overlapping with the first oxide semiconductor layer; and

a second conductive layer over the first oxide semiconductor layer,

the second transistor comprising;

a second oxide semiconductor layer;

a second source electrode layer and a second drain electrode layer each of which comprises a region overlapping with the second oxide semiconductor layer; and

a third conductive layer over the second oxide semiconductor layer,

wherein the first oxide semiconductor layer comprises a region including a crystal with a particle size greater than or equal to 1 nm and less than or equal to 20 nm,

wherein the first oxide semiconductor layer comprises a region overlapping with the first conductive layer and the second conductive layer between the first source electrode layer and the first drain electrode layer, and

wherein the second oxide semiconductor layer comprises a region overlapping with the third conductive layer between the second source electrode layer and the second drain electrode layer.

27. The display device according to claim 26, wherein an end portion of the first oxide semiconductor layer has a tapered shape.

28. The display device according to claim 26, wherein the first conductive layer contains an element selected from Al, Cr, Ta, Ti, Mo, and W.

29. The display device according to claim 26, wherein the first source electrode layer and the first drain electrode layer contain an element selected from Al, Cu, Cr, Ta, Ti, Mo, and W.

30. The display device according to claim 26, wherein the first oxide semiconductor layer has a thickness greater than or equal to 5 nm and less than or equal to 200 nm.

31. The display device according to claim 26,

wherein the first oxide semiconductor layer comprises a first region including a first crystal and a second region including a second crystal, and

wherein a crystal state of the first region is different from the crystal state of the second region.

32. The display device according to claim 26,

wherein the first oxide semiconductor layer comprises a region overlapping with the first conductive layer with a first insulating layer provided therebetween, and

wherein the first insulating layer comprises silicon oxide.

33. The display device according to claim 26,

wherein the first oxide semiconductor layer comprises a region overlapping with the second conductive layer with a second insulating layer provided therebetween, and

wherein the second insulating layer comprises silicon oxide.