Semiconductor device and method of manufacture

• US 10,868,130 B2
• Filed: 04/01/2019
• Issued: 12/15/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Yen-Ting, Lee, Wei-Yang, Yang, Feng-Cheng, Chen, Yen-Ming
• Primary Examiner(s): Schoenholtz, J. E.
• Application Number:
  US16/371,498
• Publication Number:
  US 20200135880A1
• Time in Patent Office: 624 Days
• Field of Search: None
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02167 the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/4991 comprising an air gap
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A semiconductor device including a gaseous spacer and a method for forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer over the first gate spacer; removing a portion of the second gate spacer, at least a portion of the second gate spacer remaining; removing the first gate spacer to form a first opening; and after removing the first gate spacer, removing the remaining portion of the second gate spacer through the first opening.

Claims

1. A method comprising:

forming a gate stack over a substrate;

forming a first gate spacer on sidewalls of the gate stack;

forming a second gate spacer over the first gate spacer;

removing a first portion of the second gate spacer, wherein a second portion of the second gate spacer remains;

removing a first portion of the first gate spacer to form an opening; and

after removing the first portion of the first gate spacer, removing the second portion of the second gate spacer through the opening.

2. The method of claim 1, wherein the second gate spacer comprises silicon nitride.

3. The method of claim 2, wherein the first gate spacer comprises silicon oxide.

4. The method of claim 1, wherein the first portion of the first gate spacer and the second portion of the second gate spacer are removed by etching using vapor-phase hydrogen fluoride.

5. The method of claim 1, further comprising epitaxially growing source/drain regions on opposite sides of the gate stack, wherein the second portion of the second gate spacer is disposed between the source/drain regions and the substrate.

6. The method of claim 1, further comprising epitaxially growing source/drain regions on opposite sides of the gate stack after removing the first portion of the second gate spacer, wherein the source/drain regions are epitaxially grown before removing the first portion of the first gate spacer.

7. The method of claim 1, further comprising replacing the gate stack with a metal gate before removing the first portion of the first gate spacer.

8. The method of claim 7, wherein the first portion of the first gate spacer and the second portion of the second gate spacer are removed by dry etching.

9. A method comprising:

forming a gate stack over a semiconductor substrate;

forming a gate spacer on sidewalls of the gate stack;

epitaxially growing source/drain regions on opposite sides of the gate stack;

removing at least a portion of the gate spacer to form an opening; and

depositing a dielectric layer sealing the opening and defining a gaseous spacer on sidewalls of the gate spacer.

10. The method of claim 9, wherein a first portion of the gate spacer is removed before epitaxially growing the source/drain regions and a second portion of the gate spacer is removed after epitaxially growing the source/drain regions.

11. The method of claim 10, wherein forming the gate spacer comprises depositing a first gate spacer layer over the gate stack, depositing a second gate spacer layer over the first gate spacer layer, and depositing a third gate spacer layer over the second gate spacer layer, the first gate spacer layer, the second gate spacer layer, and the third gate spacer layer each comprising different materials.

12. The method of claim 11, wherein the first gate spacer layer comprises silicon carbon nitride, the second gate spacer layer comprises silicon nitride, and the third gate spacer layer comprises silicon oxide.

13. The method of claim 11, wherein the first portion comprises a portion of the third gate spacer layer.

14. The method of claim 13, wherein the second portion comprises the second gate spacer layer and a remaining portion of the third gate spacer layer.

15. A semiconductor device comprising:

a gate stack over a semiconductor substrate;

a first gate spacer disposed on sidewalls of the gate stack;

a contact etch stop layer adjacent the first gate spacer;

a gaseous spacer disposed between the gate stack and the contact etch stop layer in a direction parallel with a major surface of the semiconductor substrate; and

an epitaxial source/drain region in the semiconductor substrate, wherein at least a portion of the gaseous spacer extends between the epitaxial source/drain region and the semiconductor substrate.

16. The semiconductor device of claim 15, wherein the gaseous spacer comprises ammonia (NH₃) and at least one of silane (SiH₄), dichlorosilane (SiH₂Cl₂), or silicon tetrachloride (SiCl₄).

17. The semiconductor device of claim 15, further comprising a first dielectric layer over the epitaxial source/drain region, wherein at least a portion of a boundary of the gaseous spacer is defined by the first dielectric layer.

18. The semiconductor device of claim 17, wherein the gaseous spacer is disposed vertically between the first dielectric layer and the first gate spacer, and wherein the gaseous spacer is disposed horizontally between the contact etch stop layer and the first gate spacer.

19. The semiconductor device of claim 18, wherein the first dielectric layer and the contact etch stop layer comprise silicon carbon nitride, and wherein the first gate spacer comprises silicon carbon nitride.

20. The semiconductor device of claim 15, wherein the gaseous spacer has a thickness of from 1 nm to 10 nm.