Semiconductor device

• US 10,872,890 B2
• Filed: 02/12/2018
• Issued: 12/22/2020
• Est. Priority Date: 12/17/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Che-Cheng, Lin, Chih-Han, Tseng, Horng-Huei
• Primary Examiner(s): Chin, Edward
• Application Number:
  US15/894,825
• Publication Number:
  US 20180175030A1
• Time in Patent Office: 1,044 Days
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A semiconductor device includes a substrate, a core device disposed above the substrate, and an input/output (I/O) device disposed above the substrate. The core device includes a first gate electrode having a bottom surface and a sidewall that define a first interior angle therebetween. The first interior angle is an obtuse angle. The I/O device includes a second gate electrode having a bottom surface and a sidewall that define a second interior angle therebetween. The second interior angle is greater than the first interior angle.

Claims

1. A semiconductor device comprising:

a substrate;

a core device over the substrate and comprising a first gate electrode having a bottom surface and a sidewall, wherein the bottom surface of the first gate electrode and the sidewall of the first gate electrode define inside the first gate electrode a first interior angle, and the first interior angle is an obtuse angle; and

an input/output (I/O) device over the substrate and comprising a second gate electrode having a bottom surface and a sidewall, wherein the bottom surface of the second gate electrode and the sidewall of the second gate electrode define inside the second gate electrode a second interior angle, and the second interior angle is greater than the first interior angle.

2. The semiconductor device of claim 1, wherein the bottom surface of the first gate electrode has a bottom width and the first gate electrode includes a top surface that has a top width and the top width is greater than the bottom width.

3. The semiconductor device of claim 1, wherein the bottom surface of the second gate electrode has a bottom width and the second gate electrode includes a top surface that has a top width and the top width is greater than the bottom width.

4. The semiconductor device of claim 1, wherein the I/O device further comprises a spacer on the sidewall of the second gate electrode, and a bottom width of a bottom surface of the spacer is greater than a top width of a top surface of the spacer.

5. The semiconductor device of claim 1, wherein the core device further comprises a spacer on the sidewall of the first gate electrode, and a bottom width of a bottom surface of the spacer is greater than a top width of a top surface of the spacer.

6. A semiconductor device comprising:

a substrate;

a core device over the substrate and comprising a first gate electrode having a bottom surface and a sidewall, wherein the bottom surface of the first gate electrode and the sidewall of the first gate electrode define inside the first gate electrode a first interior angle; and

an input/output (I/O) device over the substrate and comprising a second gate electrode having a bottom surface and a sidewall, wherein the bottom surface of the second gate electrode and the sidewall of the second gate electrode define inside the second gate electrode a second interior angle, and the second interior angle and the first interior angle both are obtuse angles but have different values.

7. The semiconductor device of claim 6, wherein the bottom surface of the first gate electrode has a first bottom width, the bottom surface of the second gate electrode has a second bottom width, and the second bottom width is greater than the first bottom width.

8. The semiconductor device of claim 6, wherein the first gate electrode includes a top surface that has a first top width, the second gate electrode includes a top surface that has a second top width, and the second top width is greater than the first top width.

9. The semiconductor device of claim 6, wherein a difference between widths of the bottom surface and a top surface of the second gate electrode is greater than a difference between widths of the bottom surface and a top surface of the first gate electrode.

10. The semiconductor device of claim 6, wherein the second interior angle is greater than the first interior angle.

11. The semiconductor device of claim 6, wherein the I/O device further comprises a spacer on a sidewall of the second gate electrode, and a bottom width of a bottom surface of the spacer is greater than a top width of a top surface of the spacer.

12. A semiconductor device comprising:

a substrate;

a core device over the substrate and comprising a first gate electrode having a top surface and a bottom surface; and

an input/output (I/O) device over the substrate and comprising a second gate electrode having a top surface and a bottom surface, wherein a width of the top surface of the first gate electrode is less than a width of the top surface of the second gate electrode, and a width of the bottom surface of the second gate electrode is less than the width of the top surface of the second gate electrode.

13. The semiconductor device of claim 12, wherein a width of the bottom surface of the first gate electrode is smaller than the width of the top surface of the first gate electrode.

14. The semiconductor device of claim 12, wherein a width of the bottom surface of the first gate electrode is greater than the width of the top surface of the first gate electrode.

15. The semiconductor device of claim 12, wherein a width of the bottom surface of the first gate electrode is substantially equal to the width of the top surface of the first gate electrode.

16. The semiconductor device of claim 12, wherein the core device further comprises a semiconductor fin disposed between the first gate electrode and the substrate.

17. The semiconductor device of claim 12, wherein the I/O device further comprises a semiconductor fin disposed between the second gate electrode and the substrate.

18. The semiconductor device of claim 12, wherein the I/O device further comprises a spacer on a sidewall of the second gate electrode, and a bottom width of a bottom surface of the spacer is greater than a top width of a top surface of the spacer.

19. The semiconductor device of claim 12, wherein the core device further comprises a spacer on a sidewall of the first gate electrode, and a bottom width of a bottom surface of the spacer is greater than a top width of a top surface of the spacer.

20. The semiconductor device of claim 12, wherein a width of the bottom surface of the first gate electrode minus the width of the top surface of the first gate electrode is greater than the width of the bottom surface of the second gate electrode minus the width of the top surface of the second gate electrode.