Pulse width compensation circuit and a semiconductor apparatus using the pulse width compensation circuit

• US 10,884,486 B2
• Filed: 11/20/2018
• Issued: 01/05/2021
• Est. Priority Date: 04/19/2018
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Park, Min Soo, Chi, Sung Soo
• Primary Examiner(s): Patel, Nimesh G
• Application Number:
  US16/196,995
• Publication Number:
  US 20190324524A1
• Time in Patent Office: 777 Days
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: H03K 5/04 by increasing duration; by decreasing duration
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation

Abstract

A pulse width compensation circuit may include a voltage control circuit and a pulse width adjustment circuit. The voltage control circuit may sense a voltage level of a first power supply voltage and generate a voltage control signal. The pulse width adjustment circuit may generate an output signal by changing a pulse width of an input signal based on the voltage control signal.

Claims

1. A pulse width compensation circuit comprising:

a voltage control circuit configured to generate a voltage control signal by sensing a voltage level of a first power supply voltage;

a first compensation circuit configured to generate a first buffer control signal based on an input signal, and configured to change any one of a low voltage level and a high voltage level of the first buffer control signal based on the voltage control signal;

a first buffer configured to generate a compensation signal based on the first buffer control signal;

a second compensation circuit configured to generate a second buffer control signal based on the compensation signal, and configured to change a voltage level which is complementary to a voltage level changed by the first compensation circuit, among a low voltage level and a high voltage level of the second buffer control signal, based on the voltage control signal; and

a second buffer configured to generate an output signal based on the second buffer control signal.

2. The pulse width compensation circuit according to claim 1,

wherein the first compensation circuit comprises:

a first pull-up driver configured to pull-up drive a first output node to a voltage level of the first power supply voltage based on the input signal;

a first pull-down driver configured to pull-down drive a pull-down node to a voltage level of a second power supply voltage based on the input signal; and

a low voltage level raising circuit configured to raise a voltage level of the pull-down node based on the voltage control signal, and configured to provide a raised voltage to the first output node, and

wherein the first buffer control signal is outputted from the first output node.

3. The pulse width compensation circuit according to claim 2,

wherein the second compensation circuit comprises:

a second pull-up driver configured to pull-up drive a pull-up node to a voltage level of the first power supply voltage based on the compensation signal;

a high voltage level lowering circuit configured to lower a voltage level of the pull-up node based on the voltage control signal, and configured to provide a lowered voltage to a second output node; and

a second pull-down driver configured to pull-down drive the second output node to the second power supply voltage based on the compensation signal, and

wherein the second buffer control signal is outputted from the second output node.

4. The pulse width compensation circuit according to claim 1,

wherein the first compensation circuit comprises:

a first pull-up driver configured to pull-up drive a pull-up node to a voltage level of the first power supply voltage based on the input signal;

a high voltage level lowering circuit configured to lower a voltage level of the pull-up node based on the voltage control signal, and configured to provide a lowered voltage to a first output node; and

a first pull-down driver configured to pull-down drive the first output node to a second power supply voltage based on the input signal, and

wherein the first buffer control signal is outputted from the first output node.

5. The pulse width compensation circuit according to claim 4,

wherein the second compensation circuit comprises:

a second pull-up driver configured to pull-up drive a second output node to a voltage level of the first power supply voltage based on the compensation signal;

a second pull-down driver configured to pull-down drive a pull-down node to a voltage level of the second power supply voltage based on the compensation signal; and

a low voltage level raising circuit configured to raise a voltage level of the pull-down node based on the voltage control signal, and provide a raised voltage to the second output node, and

wherein the second buffer control signal is outputted from the second output node.

6. A semiconductor apparatus comprising:

a voltage control circuit configured to generate at least one voltage control signal by sensing a voltage level of a first power supply voltage;

a pulse width adjustment circuit configured to generate an output signal by changing the pulse width of an input signal based on the at least one voltage control signal, wherein the pulse width adjustment circuit comprises;

a first compensation circuit configured to generate a first buffer control signal based on the input signal, and configured to change anyone of a low voltage level and a high voltage level of the first buffer control signal based on the at least one voltage control signal;

a first buffer configured to generate a compensation signal based on the first buffer control signal;

a second compensation circuit configured to generate a second buffer control signal based on the compensation signal, and configured to change a voltage level which is complementary to a voltage level changed by the first compensation circuit, among a low voltage level and a high voltage level of the second buffer control signal, based on the at least one voltage control signal; and

a second buffer configured to generate the output signal based on the second buffer control signal; and

an internal circuit configured to supply an operation voltage based on the output signal.

7. The semiconductor apparatus according to claim 6, wherein the pulse width adjustment circuit generates the output signal which has a wide pulse width when the voltage level of the first power supply voltage is lower than a target voltage level, and generates the output signal which has a narrow pulse width when the voltage level of the first power supply voltage is higher than the target voltage level.

8. The semiconductor apparatus according to claim 6, wherein the pulse width adjustment circuit generates the output signal by changing an enable period of the input signal based on the at least one voltage control signal.

9. The semiconductor apparatus according to claim 6,

wherein the first compensation circuit comprises:

a first pull-up driver configured to pull-up drive a first output node to a voltage level of the first power supply voltage based on the input signal;

a first pull-down driver configured to pull-down drive a pull-down node to a voltage level of a second power supply voltage based on the input signal; and

a low voltage level raising circuit configured to raise a voltage level of the pull-down node based on the at least one voltage control signal, and provide a raised voltage to the first output node, and

wherein the first buffer control signal is outputted from the first output node.

10. The semiconductor apparatus according to claim 9, wherein the low voltage level raising circuit comprises:

a plurality of transistors coupled in series between the first output node and the pull-down node, wherein each transistor of the plurality of transistors is configured to be turned on based on an assigned voltage control signal of the at least one voltage control signal; and

a plurality of resistors coupled in parallel with the plurality of transistors between the first output node and the pull-down node.

11. The semiconductor apparatus according to claim 9, wherein the low voltage level raising circuit comprises:

a first plurality of transistors coupled between the first output node and the pull-down node, wherein each transistor of the first plurality of transistors is configured to be turned on based on an assigned voltage control signal of the at least one voltage control signal; and

a second plurality of transistors coupled in parallel with the first plurality of transistors between the first output node and the pull-down node, wherein each transistor of the second plurality of transistors is configured to be turned on based on a complementary signal of an assigned voltage control signal of the at least one voltage control signal.

12. The semiconductor apparatus according to claim 9,

wherein the second compensation circuit comprises:

a second pull-up driver configured to pull-up drive a pull-up node to a voltage level of the first power supply voltage based on the compensation signal;

a high voltage level lowering circuit configured to lower a voltage level of the pull-up node based on the at least one voltage control signal, and configured to provide a lowered voltage to a second output node; and

a second pull-down driver configured to pull-down drive the second output node to the second power supply voltage based on the compensation signal, and

wherein the second buffer control signal is outputted from the second output node.

13. The semiconductor apparatus according to claim 12, wherein the high voltage level lowering circuit comprises:

a plurality of transistors coupled in series between the pull-up node and the second output node, wherein each transistor of the plurality of transistors is configured to be turned on based on an assigned voltage control signal of the at least one voltage control signal; and

a plurality of resistors coupled in parallel with the plurality of transistors between the pull-up node and the second output node.

14. The semiconductor apparatus according to claim 12, wherein the high voltage level lowering circuit comprises:

a first plurality of transistors coupled between the pull-up node and the second output node, wherein each transistor of the first plurality of transistors is configured to be turned on based on a complementary signal of an assigned voltage control signal of the at least one voltage control signal; and

a second plurality of transistors coupled in parallel with the first plurality of transistors between the pull-up node and the second output node, wherein each transistor of the second plurality of transistors is configured to be turned on based on an assigned voltage control signal of the at least one voltage control signal.

15. A pulse width compensation circuit comprising:

a voltage control circuit configured to generate a voltage control signal by sensing a voltage level of a first power supply voltage;

a first compensation circuit configured to receive an input signal to generate a first buffer control signal, and configured to change an enable period of the first buffer control signal based on the voltage control signal;

a first buffer configured to generate a compensation signal based on the first buffer control signal;

a second compensation circuit configured to receive the compensation signal to generate a second buffer control signal, and configured to change an enable period of the second buffer control signal based on the voltage control signal; and

a second buffer configured to generate an output signal based on the second buffer control signal.