Multi-level inverter

• US 10,886,831 B2
• Filed: 05/08/2020
• Issued: 01/05/2021
• Est. Priority Date: 03/26/2014
• Status: Active Grant

• Current Assignee: Solaredge Technologies Incorporated
• Original Assignee: Solaredge Technologies Incorporated
• Inventors: Yoscovich, Ilan, Glovinsky, Tzachi, Sella, Guy, Galin, Yoav
• Primary Examiner(s): Moody, Kyle J
• Assistant Examiner(s): Jackson, Lakaisha
• Application Number:
  US16/869,994
• Publication Number:
  US 20200266697A1
• Time in Patent Office: 242 Days
• CPC Class Codes: H02M 1/0054 Transistor switching losses periodically suspending operation of switching converter in low power mode H02M1/0035
• CPC Class Codes: H02M 1/0095 Hybrid converter topologies, e.g. NPC mixed with flying capacitor, thyristor converter mixed with MMC or charge pump mixed with buck
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 1/126 using passive filters
• CPC Class Codes: H02M 1/143 using compensating arrangements for reducing noise from the supply in transmission systems H04B15/005
• CPC Class Codes: H02M 7/483 Converters with outputs that each can have more than two voltages levels
• CPC Class Codes: H02M 7/4833 Capacitor voltage balancing
• CPC Class Codes: H02M 7/4835 comprising two or more cells, each including a switchable capacitor, the capacitors having a nominal charge voltage which corresponds to a given fraction of the input voltage, and the capacitors being selectively connected in series to determine the instantaneous output voltage
• CPC Class Codes: H02M 7/4837 Flying capacitor converters
• CPC Class Codes: H02M 7/537 using semiconductor devices only, e.g. single switched pulse inverters

Abstract

A multi-level inverter having one or more banks, each bank containing a plurality of low voltage MOSFET transistors. A processor configured to switch the plurality of low voltage MOSFET transistors in each bank to switch at multiple times during each cycle.

Claims

1. A single phase multilevel inverter comprising:

first and second DC inputs configured to receive a DC voltage;

first and second AC outputs configured to output an AC voltage having a first frequency;

a first circuit comprising first and second input terminals, a first flying capacitor and a first voltage output terminal coupled to the first AC output;

a second circuit comprising third and fourth input terminals, a second flying capacitor and a second voltage output terminal coupled to the second AC output; and

a first plurality of switches configured to operate at the first frequency and a second plurality of switches configured to operate at the first frequency;

wherein;

during a first half cycle of the AC voltage, the first plurality of switches is configured to connect the first DC input to the first input terminal, the second DC input to the fourth input terminal, and the second input terminal to the third input terminal; and

during a second half cycle of the AC voltage, the second plurality of switches is configured to connect the first DC input to the third input terminal, the second DC input to the second input terminal, and the fourth input terminal to the first input terminal.

2. The single phase multilevel inverter of claim 1, further configured to switch the first plurality of switches complementary to the second plurality of switches.

3. The single phase multilevel inverter of claim 1, wherein the first plurality of switches is configured to connect and disconnect the second input terminal to the third input terminal with mutual dead time to the second plurality of switches being configured to connect and disconnect the fourth input terminal to the first input terminal.

4. The single phase multilevel inverter of claim 1, wherein:

the second plurality of switches comprises a first switch connected between an intersection point and the first input terminal, and a fourth switch connected between the intersection point and the fourth input terminal; and

the first plurality of switches comprises a second switch connected between the intersection point and the second input terminal, and a third switch connected between the intersection point and the third input terminal.

5. The single phase multilevel inverter of claim 1, wherein:

the first plurality of switches comprises at least one first switch connected between the second input terminal and the third input terminal; and

the second plurality of switches comprises at least one second switch connected between the fourth input terminal and the first input terminal.

6. The single phase multilevel inverter of any of claim 1, wherein:

the first plurality of switches comprises a first high switch connected between the first DC input and the first input terminal, and a first low switch connected between the second DC input and the second input terminal;

the second plurality of switches comprises a second high switch connected between the first DC input and the third input terminal, and a second low switch connected between the second DC input and the fourth input terminal; and

wherein

the single phase multilevel inverter further comprises a controller configured to control the first high switch and the second low switch to be on during the first half cycle and to be off during the second half cycle, and the first low switch and the second high switch to be off during the first half cycle and to be on during the second half cycle.

7. The single phase multilevel inverter of claim 1, further comprising:

a first inductor connected between the first voltage output terminal and the first AC output; and

a second inductor connected between the second voltage output terminal and the second AC output.

8. The single phase multilevel inverter of claim 1, wherein:

the single phase multilevel inverter is configured to generate a first sine wave voltage on the first AC output and a second sine wave voltage on the second AC output;

the first sine wave voltage is 180 degrees phase shifted from the second sine wave voltage; and

the AC voltage is output as a voltage difference between the first and the second sine wave voltages.

9. The single phase multilevel inverter of claim 1, wherein the first plurality of switches and the second plurality of switches are configured to share current between the first circuit and the second circuit such that ripple voltage is removed across the first and the second input terminals and removed across the third and the fourth input terminals.

10. The single phase multilevel inverter of claim 1, wherein:

the first circuit comprises a third plurality of switches, the second circuit comprises a fourth plurality of switches, and the third plurality of switches and the fourth plurality of switches are configured to switch at a second frequency that is greater than the first frequency.

11. The single phase multilevel inverter of claim 10, wherein each switch of the third plurality of switches and the fourth plurality of switches is switched according to a duty-cycle ratio.

12. The single phase multilevel inverter of claim 11, wherein

a first connection established by the first plurality of switches between the second and the third input terminals includes a first filter inductor, and

a second connection established by the second plurality of switches between the fourth and the first input terminals includes a second filter inductor, said filter inductors being configured to filter current at the second frequency from flowing between the first and the second circuits.

13. The single phase multilevel inverter of claim 11, further comprising a controller,

wherein:

the first circuit comprises a third plurality of switches, the second circuit comprises a fourth plurality of switches, the third plurality of switches corresponding one-to-one with the fourth plurality of switches; and

the controller is configured to switch the third plurality of switches and the fourth plurality of switches at a second frequency that is greater than the first frequency such that, during each cycle of the second frequency, each switch of the third plurality of switches turns on and off in a complementary manner to its corresponding switch of the fourth plurality of switches.

14. The single phase multilevel inverter of claim 11, further comprising a controller,

wherein:

the first circuit comprises a third plurality of switches, and the second circuit comprises a fourth plurality of switches; and

during the first and the second half cycles of the AC voltage, the controller is configured to switch the third plurality of switches and the fourth plurality of switches at a second frequency that is greater than the first frequency and that is greater than 16 kHz.

15. The single phase multilevel inverter of claim 11, wherein the first frequency is 50 Hz or 60 Hz.

16. The single phase multilevel inverter of claim 10,

wherein the third plurality of switches comprises a first bank of series connected switches and a second bank of series connected switches;

wherein the fourth plurality of switches comprises a third bank of series connected switches and a fourth bank of series connected switches; and

wherein each switch of the first bank and a respective switch of the fourth bank receives a first control input, and each switch of the second bank and a respective switch of the third bank receives a second control input.

17. The single phase multilevel inverter of claim 16, wherein the second control input is an inverted version of the first control input.

18. The single phase multilevel inverter of claim 16, wherein N is a number of the series connected switches of the first bank;

and each switch of the series connected switches of the first bank is switched by a control signal shifted sequentially by 1/N of a switching period.

19. The single phase multilevel inverter of claim 10,

wherein the third plurality of switches comprises a first bank of series connected switches and, a second bank of series connected switches;

wherein the fourth plurality of switches comprises a third bank of series connected switches and, a fourth bank of series connected switches; and

wherein each switch of the first bank and a corresponding switch of the fourth bank is switched at a first common duty-cycle and at the second frequency, and each switch of the second bank and a corresponding switch of the third bank is switched at a second common duty-cycle and at the second frequency.

20. The single phase multilevel inverter of claim 19, wherein the second common duty-cycle is complementary with respect to the first common duty-cycle.

21. The single phase multilevel inverter of claim 10,

wherein the third plurality of switches comprises a first bank of two series connected switches and, a second bank of two series connected switches;

and

wherein the fourth plurality of switches comprises a third bank of two series connected switches and, a fourth bank of two series connected switches;

wherein in each of the first, second, third and fourth banks, each switch of the two series connected switches is switched by a control signal shifted by 180 degrees.

22. The single phase multilevel inverter of claim 10,

wherein the third plurality of switches comprises a first bank of series connected switches and a second bank of series connected switches;

wherein the fourth plurality of switches comprises a third bank of series connected switches and a fourth bank of series connected switches; and

wherein in each of the first, second, third and fourth banks, each switch of the series connected switches is switched at a common duty-cycle.

23. A method comprising:

generating an AC voltage having a first frequency with a single phase multilevel inverter comprising first and second DC inputs, first and second AC outputs, a first plurality of switches and a second plurality of switches, a first circuit having first and second input terminals and a first voltage output terminal coupled to the first AC output, and a second circuit having third and fourth input terminals and a second voltage output terminal coupled to the second AC output;

wherein the generating comprises;

receiving a DC voltage across the first and the second DC inputs; and

switching the first plurality of switches and the second plurality of switches at the first frequency, including;

a) closing, during first half cycles of the AC voltage, the first plurality of switches to connect the first DC input to the first input terminal, the second DC input to the fourth input terminal, and the second input terminal to the third input terminal; and

b) closing, during second half cycles of the AC voltage, the second plurality of switches to connect the first DC input to the third input terminal, the second DC input to the second input terminal, and the fourth input terminal to the first input terminal.