Stacked FET switch bias ladders

  • US 10,886,911 B2
  • Filed: 03/28/2018
  • Issued: 01/05/2021
  • Est. Priority Date: 03/28/2018
  • Status: Active Grant
First Claim
Patent Images

1. A FET switch stack, including:

  • (a) a plurality of series-coupled FETs having a first FET configured to be coupled to a radio frequency (RF) signal input;

    (b) a first gate resistor ladder including a plurality of parallel-connected constant-valued resistors each coupled to the gate of one corresponding FET; and

    (c) a second gate bias resistor ladder including a plurality of series-connected variable-valued resistors each coupled to one corresponding constant-valued resistor of the first gate resistor ladder and having resistive values that taper from higher resistive values to lower resistive values, with the higher resistive values located near the RF signal input to the first FET.

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