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Sense circuit for piezoresistive sensor, circuit including array of piezoresistive sensors, and operation method thereof

  • US 10,890,607 B2
  • Filed: 11/30/2018
  • Issued: 01/12/2021
  • Est. Priority Date: 04/04/2018
  • Status: Active Grant
First Claim
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1. A sense circuit for a piezoresistive sensor, comprising:

  • an energy storage circuit coupled to the piezoresistive sensor via a first node;

    a charge control circuit coupled to the first node and configured to charge the energy storage circuit to a predetermined potential;

    a discharge control circuit configured to allow the energy storage circuit to discharge through the piezoresistive sensor; and

    a readout circuit coupled to the first node and configured to output a sensed voltage based on a level of charges stored by the energy storage circuit,wherein the piezoresistive sensor has a first end configured to receive a first voltage,the energy storage circuit has a first end configured to receive a second voltage, and a second end coupled to the first node,the charge control circuit is configured to charge the energy storage circuit such that the first node is charged to the predetermined potential;

    the discharge control circuit is coupled to the first node and a second end of the piezoresistive sensor, respectively, configured to control a discharge path for the energy storage circuit, which includes the piezoresistive sensor, to be turned on or off, so that the energy storage circuit can be discharged through the piezoresistive sensor in the case that the discharge path is turned on; and

    the readout circuit is coupled to the first node and configured to output the sensed voltage according to the level of the charges stored by the energy storage circuit in response to a sense control signal,wherein the readout circuit comprises;

    a first switch transistor having a first end coupled to the first node, and a control end to receive the sense control signal;

    a first capacitive device having a first end coupled to a second end of the first switch transistor; and

    an operational amplifier having a first input coupled to the second end of the first switch transistor, a second input to receive a reference voltage, and an output coupled to a second end of the first capacitive device.

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