Memory management method, memory storage device and memory control circuit unit

• US 10,892,026 B2
• Filed: 06/08/2018
• Issued: 01/12/2021
• Est. Priority Date: 04/16/2018
• Status: Active Grant

• Current Assignee: Phison Electronics Corporation
• Original Assignee: Phison Electronics Corporation
• Inventors: Lin, Wei, Liu, An-Cheng, Chen, Szu-Wei, Yang, Yu-Siang
• Primary Examiner(s): Choi, Charles J
• Application Number:
  US16/003,114
• Publication Number:
  US 20190318791A1
• Time in Patent Office: 949 Days
• Field of Search: None
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

A memory management method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: programming first data into a plurality of first memory cells in the rewritable non-volatile memory module, such that the programmed first memory cells have a plurality of states; sending a first single-stage read command sequence which indicates to read the programmed first memory cells by using a first read voltage level; obtaining first count information corresponding to the first read voltage level according to a read result corresponding to the first single-stage read command sequence; and adjusting the first read voltage level according to the first count information and default count information corresponding to the first read voltage level.

Claims

1. A memory management method for a memory storage device comprising a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of memory cells, and the memory management method comprises:

randomizing original data to generate first data, wherein the original data is from a host system and comprises data to be stored;

programming the first data into a plurality of first memory cells among the memory cells, such that the programmed first memory cells have a plurality of states, wherein each of the plurality of states corresponds to a default bit value;

sending a first single-stage read command sequence which indicates to read the programmed first memory cells by using a first read voltage level;

obtaining first count information corresponding to the first read voltage level according to a read result corresponding to the first single-stage read command sequence;

sending a second single-stage read command sequence which indicates to read the programmed first memory cells by using a plurality of second read voltage levels according to the first count information, wherein a plurality of voltage ranges are classified by the second read voltage levels;

obtaining second count information reflecting a number of at least one memory cell each having a voltage level belonging to one of the voltage ranges according to a reading result corresponding to the second single-stage read command sequence; and

adjusting the first read voltage level according to the first count information, the second count information and default count information corresponding to the first read voltage level.

2. The memory management method according to claim 1, wherein the default count information corresponding to the first read voltage level reflects a default memory cell count.

3. The memory management method according to claim 1, wherein a value of the default count information corresponding to the first read voltage level is positively correlated with a total number of the plurality of first memory cells, and the value of the default count information corresponding to the first read voltage level is negatively correlated with a total number of the plurality of states.

4. The memory management method according to claim 1, further comprising:

obtaining the default count information corresponding to the first read voltage level according to Equation (1) below;

C=i×

(N/M) 

 

(1),

wherein in Equation (1), the parameter C represents the default count information corresponding to the first read voltage level, the parameter i represents an index value corresponding to the first read voltage level, the parameter N represents a total number of the plurality of first memory cells, and the parameter M represents a total number of the plurality of states.

5. The memory management method according to claim 1, wherein the first count information corresponding to the first read voltage level reflects a number of at least one memory cell each having a voltage level that is not greater than the first read voltage level among the programmed first memory cells.

6. The memory management method according to claim 1, wherein the step of adjusting the first read voltage level according to the first count information, the second count information and the default count information corresponding to the first read voltage level comprises:

determining a first adjustment value according to the first count information and the default count information; and

adjusting the first read voltage level according to the first adjustment value and the second count information.

7. The memory management method according to claim 6, wherein the step of adjusting the first read voltage level according to the first adjustment value and the second count information comprises:

determining a second adjustment value according to the read result corresponding to the second single-stage read command sequence; and

adjusting the first read voltage level according to the first adjustment value and the second adjustment value.

8. A memory storage device comprising:

a connection interface unit configured to couple to a host system;

a rewritable non-volatile memory module comprising a plurality of memory cells; and

a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module,

wherein the memory control circuit unit is configured to randomize original data to generate first data, wherein the original data is from the host system and comprises data to be stored,

wherein the memory control circuit unit is further configured to send a write command sequence which indicates to program the first data into a plurality of first memory cells among the memory cells, such that the programmed first memory cells have a plurality of states, wherein each of the plurality of states corresponds to a default bit value,

wherein the memory control circuit unit is further configured to send a first single-stage read command sequence which indicates to read the programmed first memory cells by using a first read voltage level,

wherein the memory control circuit unit is further configured to obtain first count information corresponding to the first read voltage level according to a read result corresponding to the first single-stage read command sequence,

wherein the memory control circuit unit is further configured to send a second single-stage read command sequence which indicates to read the programmed first memory cells by using a plurality of second read voltage levels according to the first count information, wherein a plurality of voltage ranges are classified by the second read voltage levels,

wherein the memory control circuit unit is further configured to obtain second count information reflecting a number of at least one memory cell each having a voltage level belonging to one of the voltage ranges according to a reading result corresponding to the second single-stage read command sequence, and

wherein the memory control circuit unit is further configured to adjust the first read voltage level according to the first count information, the second count information and default count information corresponding to the first read voltage level.

9. The memory storage device according to claim 8, wherein the default count information corresponding to the first read voltage level reflects a default memory cell count.

10. The memory storage device according to claim 8, wherein a value of the default count information corresponding to the first read voltage level is positively correlated with a total number of the plurality of first memory cells, and the value of the default count information corresponding to the first read voltage level is negatively correlated with a total number of the plurality of states.

11. The memory storage device according to claim 8, wherein the memory control circuit unit is further configured to obtain the default count information corresponding to the first read voltage level according to Equation (1) below:

C=i×

(N/M) 

 

(1),

wherein in Equation (1), the parameter C represents the default count information corresponding to the first read voltage level, the parameter i represents an index value corresponding to the first read voltage level, the parameter N represents a total number of the plurality of first memory cells, and the parameter M represents a total number of the plurality of states.

12. The memory storage device according to claim 8, wherein the first count information corresponding to the first read voltage level reflects a number of at least one memory cell each having a voltage level that is not greater than the first read voltage level among the programmed first memory cells.

13. The memory storage device according to claim 8, wherein the operation of adjusting the first read voltage level according to the first count information, the second count information and the default count information corresponding to the first read voltage level by the memory control circuit unit comprises:

determining a first adjustment value according to the first count information and the default count information; and

adjusting the first read voltage level according to the first adjustment value and the second count information.

14. The memory storage device according to claim 13, wherein the operation of adjusting the first read voltage level according to the first adjustment value and the second count information by the memory control circuit unit comprises:

determining a second adjustment value according to the read result corresponding to the second single-stage read command sequence; and

adjusting the first read voltage level according to the first adjustment value and the second adjustment value.

15. A memory control circuit unit configured to control a rewritable non-volatile memory module comprising a plurality of memory cells, the memory control circuit unit comprising:

a host interface configured to couple to a host system;

a memory interface configured to couple to the rewritable non-volatile memory module; and

a memory management circuit coupled to the host interface and the memory interface,

wherein the memory management circuit is configured to randomize original data to generate first data, wherein the original data is from the host system and comprises data to be stored,

wherein the memory management circuit is further configured to send a write command sequence which indicates to program the first data into a plurality of first memory cells among the memory cells, such that the programmed first memory cells have a plurality of states, wherein each of the plurality of states corresponds to a default bit value,

wherein the memory management circuit is further configured to send a first single-stage read command sequence which indicates to read the programmed first memory cells by using a first read voltage level,

wherein the memory management circuit is further configured to obtain first count information corresponding to the first read voltage level according to a read result corresponding to the first single-stage read command sequence,

wherein the memory management circuit is further configured to send a second single-stage read command sequence which indicates to read the programmed first memory cells by using a plurality of second read voltage levels according to the first count information, wherein a plurality of voltage ranges are classified by the second read voltage levels,

wherein the memory management circuit is further configured to obtain second count information reflecting a number of at least one memory cell each having a voltage level belonging to one of the voltage ranges according to a reading result corresponding to the second single-stage read command sequence, and

wherein the memory management circuit is further configured to adjust the first read voltage level according to the first count information, the second count information and default count information corresponding to the first read voltage level.

16. The memory control circuit unit according to claim 15, wherein the default count information corresponding to the first read voltage level reflects a default memory cell count.

17. The memory control circuit unit according to claim 15, wherein a value of the default count information corresponding to the first read voltage level is positively correlated with a total number of the plurality of first memory cells, and the value of the default count information corresponding to the first read voltage level is negatively correlated with a total number of the plurality of states.

18. The memory control circuit unit according to claim 15, wherein the memory management circuit is further configured to obtain the default count information corresponding to the first read voltage level according to Equation (1) below:

C=i×

(N/M) 

 

(1),

wherein in Equation (1), the parameter C represents the default count information corresponding to the first read voltage level, the parameter i represents an index value corresponding to the first read voltage level, the parameter N represents a total number of the plurality of first memory cells, and the parameter M represents a total number of the plurality of states.

19. The memory control circuit unit according to claim 15, wherein the first count information corresponding to the first read voltage level reflects a number of at least one memory cell each having a voltage level that is not greater than the first read voltage level among the programmed first memory cells.

20. The memory control circuit unit according to claim 15, wherein the operation of adjusting the first read voltage level according to the first count information, the second count information and the default count info nation corresponding to the first read voltage level by the memory management circuit comprises:

determining a first adjustment value according to the first count information and the default count information; and

adjusting the first read voltage level according to the first adjustment value and the second count information.

21. The memory control circuit unit according to claim 20, wherein the operation of adjusting the first read voltage level according to the first adjustment value and the second count information by the memory management circuit comprises:

determining a second adjustment value according to the read result corresponding to the second single-stage read command sequence; and

adjusting the first read voltage level according to the first adjustment value and the second adjustment value.

22. A memory management method for a memory storage device comprising a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of memory cells, and the memory management method comprises:

in a first read mode, sending a first single-stage read command sequence which indicates to read a plurality of first memory cells being programmed based on first data that is generated by randomizing original data received from a host system among the plurality of memory cells by using a first read voltage level, wherein response information of the first single-stage read command sequence comprises first count information for adjusting the first read voltage level;

in the first read mode, sending a second single-stage read command sequence which indicates to read the programmed first memory cells by using a plurality of second read voltage levels according to the first count information, wherein a plurality of voltage ranges are classified by the second read voltage levels and response information of the second single-stage read command sequence comprises second count information for further adjusting the first read voltage level; and

in the first read mode, sending a first common read command sequence which indicates to read the plurality of first memory cells by using the adjusted first read voltage level, wherein response information of the first common read command sequence is used to generate read data requested by a host system.

23. The memory management method according to claim 22, further comprising:

in a second read mode, sending at least one second common read command sequence which indicates to read the plurality of first memory cells by using a plurality of third read voltage levels, wherein response information of the at least one second common read command sequence is used to generate the read data requested by the host system, and a number of the plurality of third read voltage levels is greater than a number of the first read voltage level.