Semiconductor wafer dicing crack prevention using chip peripheral trenches

• US 10,903,120 B2
• Filed: 09/28/2018
• Issued: 01/26/2021
• Est. Priority Date: 02/28/2017
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Zechmann, Arno, Pozzovivo, Gianmauro
• Primary Examiner(s): Pham, Long
• Application Number:
  US16/146,374
• Publication Number:
  US 20190043757A1
• Time in Patent Office: 851 Days
• Field of Search: None
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/6609 Diodes
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7783 using III-V semiconductor material

Abstract

A method includes providing a semiconductor base substrate having a substantially planar growth surface and one or more preferred crystallographic cleavage planes and an epitaxial first type III-V semiconductor layer on the planar growth surface. A first trench that vertically extends from an upper surface of the first type III-V semiconductor layer is formed at least to the planar growth surface. The first trench has a first trench length direction that is antiparallel to the one or more preferred crystallographic cleavage planes.

Claims

1. A method of forming a semiconductor device, comprising:

providing a semiconductor base substrate comprising a substantially planar growth surface and one or more crystallographic cleavage planes and an epitaxial first type III-V semiconductor layer on the planar growth surface; and

forming a first trench that vertically extends from an upper surface of the first type III-V semiconductor layer at least to the planar growth surface,

wherein the first trench has a first trench length direction that is antiparallel to the one or more crystallographic cleavage planes.

2. The method according to claim 1, wherein the first trench extends into the planar growth surface such that an indentation in the planar growth surface of the semiconductor base substrate forms the base of the first trench.

3. The method according to claim 2, further comprising:

forming at least one second trench that vertically extends from an upper surface of the first type III-V semiconductor layer at least to the planar growth surface, the second trench extending perpendicularly to the first trench and having a second trench length direction that is antiparallel to the one or more crystallographic cleavage planes.

4. The method according to claim 3, further comprising:

forming device structures in component positions of the first type III-V semiconductor layer, the component positions being arranged in a grid of rowsand columns, each of the rows and columns having a direction, wherein the direction is antiparallel with the one or more of the crystallographic cleavage planes.

5. The method according to claim 4, further comprising:

forming a cut that separates the first type III-V semiconductor layer and the base substrate into two discrete semiconductor chips,

wherein the cut is formed along a first cutting plane that is antiparallel to

the one or more crystallographic cleavage planes of the substrate.

6. The method according to claim 5, wherein the base substrate comprises an indicator feature that indicates a crystallographic orientation of the substrate, the method further comprising:

using the indicator feature to orient the first trench such that the first trench length direction extends along the plane that is antiparallel to the one or more crystallographic cleavage planes of the substrate.

7. The method according to claim 5, wherein the semiconductor base substrate comprises an indicator feature that identifies the cleavage planes of the base substrate, the method further comprising:

positioning the indicator feature such that the cleavage planes of the substrate are antiparallel and antiperpendicular to the indicator feature.

8. The method according to claim 7, wherein the semiconductor base substratecomprises silicon and has a growth surface having a <

111>

plane and the indicator feature is positioned such that <

110>

, <

011> and

<

101>

crystallographic planes of the substrate are antiparallel and antiperpendicular to the indicator feature.

9. The method according to claim 7, wherein the indicator feature is a flat edge and the method further comprises forming the first trench such that it is parallel or perpendicular to the flat edge.

10. The method according to claim 1, further comprising:

forming two first trenches extending parallel to one another along a first trench length direction, the first length direction being antiparallel to the one or more crystallographic cleavage planes of the substrate; and

forming two second trenches extending parallel to one another along a second trench length direction that is perpendicular to the first trench length direction and antiparallel to the one or more crystallographic cleavage planes of the substrate.

11. The method according to claim 10, wherein the first type III-V semiconductor layer and the substrate are cut along a first cutting plane that is parallel to the first trench length direction and between the two first trenches.

12. The method according to claim 11, wherein the two first trenches are formed to define first, second and third lateral sections of the first layer, the first lateral section being disposed on one side of the first trench, the second lateral section being disposed between the first and second trenches, and the third lateral section being disposed on one side of the second trench, and wherein the cut is formed in the second lateral section.

13. The method of claim 12, further comprising:

filling the first trench with a filler material that is different from material of the type III-V semiconductor layer, the filler material comprising any one or combination of;

a semiconductor oxide, a polycrystalline material, and a metal.