Method, device and system for control signalling in a data path module of a data stream processing engine

• US 10,942,737 B2
• Filed: 12/14/2018
• Issued: 03/09/2021
• Est. Priority Date: 12/29/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ivanov, Vladimir
• Primary Examiner(s): Metzger, Michael J
• Application Number:
  US16/221,379
• Publication Number:
  US 20190129720A1
• Time in Patent Office: 816 Days
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 15/17 using an input/output type connection, e.g. channel, I/O port
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/32 Address formation of the next instruction, e.g. by incrementing the instruction counter G06F9/38 takes precedence
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3897 with adaptable data path

Abstract

Techniques and mechanisms for exchanging control signals in a data path module of a data stream processing engine. In an embodiment, the data path module may be configured to form a set of one or more data paths corresponding to an instruction which is to be executed. In another embodiment, data processing units of the data path module may be configured to exchange one or more control signals for elastic execution of the instruction.

Claims

1. A programmable accelerator comprising:

a first data processing circuit, a second data processing circuit, and a third data processing circuit; and

a controller to receive a message from a host processor identifying an operation to be performed by the programmable accelerator, the controller, responsive to the message, to program the first data processing circuit, the second data processing circuit, and the third data processing circuit with a configuration to perform a data driven execution of the operation independently of the host processor,

wherein each of the first data processing circuit, the second data processing circuit, and the third data processing circuit includes a read port and a write port, and the configuration of the first data processing circuit, the second data processing circuit, and the third data processing circuit forms a set of one or more data paths for the operation from the ports, and

the configuration causes the first data processing circuit to send both intermediate data based on data input into the first data processing circuit and a validity control value to the second data processing circuit, and the second data processing circuit to determine a resultant of the operation on the intermediate data when receiving the intermediate data, the validity control value, and a communication from the third data processing circuit that indicates the third data processing circuit is ready to receive the resultant from the second data processing circuit.

2. The programmable accelerator of claim 1, wherein the configuration comprises a respective configuration for each of the first data processing circuit, the second data processing circuit, and the third data processing circuit.

3. The programmable accelerator of claim 1, wherein the operation is multiple atomic operations.

4. The programmable accelerator of claim 1, wherein the configuration causes the intermediate data to be read in parallel across multiple read ports of the second data processing circuit.

5. The programmable accelerator of claim 1, wherein the data driven execution is driven independent of any scheduling signal received from the controller during the data driven execution.

6. The programmable accelerator of claim 1, wherein the configuration causes the second data processing circuit to send a communication to the first data processing circuit to indicate that the second data processing circuit is ready to output the resultant.

7. The programmable accelerator of claim 6, wherein the configuration causes the first data processing circuit to flush the intermediate data in response to receipt of the communication by the first data processing circuit indicating that the second data processing circuit is ready to output the resultant.

8. The programmable accelerator of claim 1, further comprising a load store circuit, wherein the controller programs the load store circuit to perform a memory access for the operation independently of the host processor.

9. A method comprising:

receiving a message with a controller of a programmable accelerator from a host processor identifying an operation to be performed by the programmable accelerator;

programming, responsive to the message, a first data processing circuit, a second data processing circuit, and a third data processing circuit of the programmable accelerator with a configuration by the controller to perform a data driven execution of the operation independently of the host processor, wherein each of the first data processing circuit, the second data processing circuit, and the third data processing circuit includes a read port and a write port;

coupling, based on the configuration, the first data processing circuit, the second data processing circuit, and the third data processing circuit to form a set of one or more data paths for the operation from the ports;

sending, by the first data processing circuit and based on the configuration, both intermediate data based on data input into the first data processing circuit and a validity control value to the second data processing circuit; and

determining, by the second data processing circuit and based on the configuration, a resultant of the operation on the intermediate data when receiving the intermediate data, the validity control value, and a communication from the third data processing circuit that indicates the third data processing circuit is ready to receive the resultant from the second data processing circuit.

10. The method of claim 9, wherein the programming comprises sending a respective configuration to each of the first data processing circuit, the second data processing circuit, and the third data processing circuit.

11. The method of claim 9, wherein the operation is multiple atomic operations.

12. The method of claim 9, wherein the configuration causes the intermediate data to be read in parallel across multiple read ports of the second data processing circuit.

13. The method of claim 9, wherein the data driven execution is driven independent of any scheduling signal received from the controller during the data driven execution.

14. The method of claim 9, wherein the configuration causes the second data processing circuit to send a communication to the first data processing circuit to indicate that the second data processing circuit is ready to output the resultant.

15. The method of claim 14, wherein the configuration causes the first data processing circuit to flush the intermediate data in response to receipt of the communication by the first data processing circuit indicating that the second data processing circuit is ready to output the resultant.

16. The method of claim 9, further comprising programming, by the controller, a load store circuit of the programmable accelerator to perform a memory access for the operation independently of the host processor.

17. A system comprising:

a processor; and

a programmable accelerator coupled to the processor, the programmable accelerator comprising;

a first data processing circuit, a second data processing circuit, and a third data processing circuit, and

a controller to receive a message from the processor identifying an operation to be performed by the programmable accelerator, the controller, responsive to the message, to program the first data processing circuit, the second data processing circuit, and the third data processing circuit with a configuration to perform a data driven execution of the operation independently of the processor,

wherein each of the first data processing circuit, the second data processing circuit, and the third data processing circuit includes a read port and a write port, and the configuration of the first data processing circuit, the second data processing circuit, and the third data processing circuit forms a set of one or more data paths for the operation from the ports, and

the configuration causes the first data processing circuit to send both intermediate data based on data input into the first data processing circuit and a validity control value to the second data processing circuit, and the second data processing circuit to determine a resultant of the operation on the intermediate data when receiving the intermediate data, the validity control value, and a communication from the third data processing circuit that indicates the third data processing circuit is ready to receive the resultant from the second data processing circuit.

18. The system of claim 17, wherein the configuration comprises a respective configuration for each of the first data processing circuit, the second data processing circuit, and the third data processing circuit.

19. The system of claim 17, wherein the operation is multiple atomic operations.

20. The system of claim 17, wherein the configuration causes the intermediate data to be read in parallel across multiple read ports of the second data processing circuit.

21. The system of claim 17, wherein the data driven execution is driven independent of any scheduling signal received from the controller during the data driven execution.

22. The system of claim 17, wherein the configuration causes the second data processing circuit to send a communication to the first data processing circuit to indicate that the second data processing circuit is ready to output the resultant.

23. The system of claim 22, wherein the configuration causes the first data processing circuit to flush the intermediate data in response to receipt of the communication by the first data processing circuit indicating that the second data processing circuit is ready to output the resultant.

24. The system of claim 17, further comprising a load store circuit, wherein the controller programs the load store circuit to perform a memory access for the operation independently of the processor.