External compensation circuit and method, and display device

• US 10,943,536 B2
• Filed: 06/14/2019
• Issued: 03/09/2021
• Est. Priority Date: 08/31/2018
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Wang, Tangxiang, Song, Chen
• Primary Examiner(s): Earles, Bryan
• Application Number:
  US16/441,064
• Publication Number:
  US 20200074924A1
• Time in Patent Office: 634 Days
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0814 used for selection purposes, e.g. logical AND for partial update
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2320/045 Compensation of drifts in the characteristics of light emitting or modulating elements
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element

Abstract

Provided are an external compensation circuit and method, and display device in the field of display techniques. The external compensation circuit includes a regulation sub-circuit that may collect a driving current loaded to a light-emitting unit and a reference current from a reference current source, and regulate potentials at two nodes connected to a compensation sub-circuit according to the collected current, to enable the compensation sub-circuit to calibrate a data signal to be input to a pixel circuit according to a potential difference between the two nodes.

Claims

1. An external compensation circuit, comprising:

a regulation sub-circuit, and a compensation sub-circuit;

wherein

the regulation sub-circuit is connected to a reference current source, a current detection terminal of a pixel circuit, a first node and a second node respectively, and configured to regulate a potential at the first node and a potential at the second node according to a reference current provided by the reference current source, and configured to regulate the potential at the second node according to a collected driving current loaded to a light-emitting unit by the pixel circuit;

the compensation sub-circuit is connected to the first node, the second node, and a data signal terminal of the pixel circuit respectively, and configured to calibrate a data signal to be input to the pixel circuit according to a potential difference between the first node and the second node, and input the calibrated data signal to the pixel circuit; and

the regulation sub-circuit comprises;

a current amplifying portion and a potential regulating portion;

wherein

the current amplifying portion is connected to the reference current source, the current detection terminal of the pixel circuit, a third node and a fourth node respectively, and configured to amplify a collected current, and input the current that is amplified to the potential regulating portion through the third node and the fourth node, wherein the current is the reference current or the driving current; and

the potential regulating portion is connected to the first node, the second node, the third node and the fourth node respectively, and configured to regulate the potential at the first node and the potential at the second node according to the reference current that is amplified, and regulate the potential at the second node according to the driving current that is amplified.

2. The circuit according to claim 1, wherein the current amplifying portion comprises:

a first amplifier, a first resistance, a second resistance, a first switch, a second switch, a third switch, and a fourth switch;

wherein

a first input terminal of the first amplifier is connected to one terminal of the third switch, a second input terminal of the first amplifier is connected to a fifth node, and an output terminal of the first amplifier is connected to the third node, wherein another terminal of the third switch is connected to a direct current power source terminal;

one terminal of the first resistance is connected to one terminal of the second switch, and another terminal of the first resistance is connected to the fourth node, wherein another terminal of the second switch is connected to the fifth node;

one terminal of the second resistance is connected to the fourth node, and another terminal of the second resistance is connected to the direct current power source terminal;

one terminal of the first switch is connected to the fifth node, and another terminal of the first switch is connected to the third node; and

a first terminal of the fourth switch is connected to the fifth node, a second node of the fourth switch is connected to the reference current source, and a third terminal of the fourth switch is connected to the current detection terminal of the pixel circuit.

3. The circuit according to claim 1, wherein the potential regulating portion comprises:

a first transistor, a second transistor, a capacitor, and a fifth switch;

wherein

a gate of the first transistor is connected to the third node, a first electrode of the first transistor is connected to the second node, and a second electrode of the first transistor is connected to the fourth node;

a gate of the second transistor is connected to the first node, a first electrode of the second transistor is connected to one terminal of the capacitor, and a second electrode of the second transistor is connected to the second node, wherein another terminal of the capacitor is connected to the first node; and

one terminal of the fifth switch is connected to the first node, and another terminal of the fifth switch is connected to the second node.

4. The circuit according to claim 1, wherein the compensation sub-circuit comprises:

a control portion and a calibration portion;

wherein

the control portion is connected to the first node, the second node, and the calibration portion respectively, and configured to determine a compensation amount of a data signal according to the potential difference between the first node and the second node, and input the compensation amount to the calibration portion; and

the calibration portion is further connected to the data signal terminal of the pixel circuit, and configured to calibrate the data signal to be input the pixel circuit according to the compensation amount received, and input a calibrated data signal to the pixel circuit.

5. The circuit according to claim 4, wherein the compensation sub-circuit further comprises:

a storage portion connected to the control portion;

the storage portion is configured to store a corresponding relation between a potential difference and a compensation amount; and

the control portion is configured to determine, according to the corresponding relation, a compensation amount corresponding to the potential difference between the first node and the second node as the compensation amount of the data signal.

6. The circuit according to claim 1, further comprising:

a comparison sub-circuit;

wherein

the comparison sub-circuit is connected to the first node, the second node, and the compensation sub-circuit respectively, and configured to compare the potential at the first node with the potential at the second node, and input a comparison result to the compensation sub-circuit; and

the compensation sub-circuit is configured to calibrate, when the potential at the first node is determined not to be equal to the potential at the second node according to the comparison result, the data signal to be input to the pixel circuit according to the potential difference between the first node and the second node.

7. The circuit according to claim 6, wherein the comparison sub-circuit further comprises:

a comparator;

wherein

a first input terminal of the comparator is connected to the first node, a second input terminal of the comparator is connected to the second node, and an output terminal of the comparator is connected to the compensation sub-circuit.

8. The circuit according to claim 1, further comprising:

an amplification sub-circuit;

wherein

the amplification sub-circuit is connected to the first node, the second node, and the compensation sub-circuit respectively, and configured to amplify the potential difference and input amplified potential difference to the compensation sub-circuit.

9. The circuit according to claim 8, wherein the amplification sub-circuit comprises:

a second amplifier;

wherein

a first input terminal of the second amplifier is connected to the first node, a second input terminal of the second amplifier is connected to the second node, and an output terminal of the second amplifier is connected to the compensation sub-circuit.

10. The circuit according to claim 1, further comprising:

a digital-to-analog converting sub-circuit;

wherein

the digital-to-analog converting sub-circuit is connected to the compensation sub-circuit and the data signal terminal of the pixel circuit respectively, and configured to convert the calibrated data signal input by the compensation sub-circuit into an analog signal and input the analog signal to the pixel circuit.

11. The circuit according to claim 10, wherein the regulation sub-circuit is further connected to the data signal terminal of the pixel circuit;

and the digital-to-analog converting sub-circuit is connected to the data signal terminal of the pixel circuit through the regulation sub-circuit;

the digital-to-analog converting sub-circuit comprises;

a digital-to-analog converter and a sixth switch;

wherein

one terminal of the digital-to-analog converter is connected to the compensation sub-circuit, and another terminal of the digital-to-analog converter is connected to one terminal of the sixth switch; and

another terminal of the sixth switch is connected to the regulation sub-circuit.

12. The circuit according to claim 2, further comprising a comparison sub-circuit, an amplification sub-circuit, and a digital-to-analog converting sub-circuit;

wherein the potential regulating portion comprises a first transistor, a second transistor, a capacitor, and a fifth switch;

the comparison sub-circuit comprises a comparator;

the amplification sub-circuit comprises a second amplifier;

the compensation sub-circuit comprises a control portion, a calibration portion, and a storing portion; and

the digital-to-analog converting sub-circuit comprises a digital-to-analog converter and a sixth switch;

wherein

a gate of the first transistor is connected to the third node, a first electrode of the first transistor is connected to the second node, and a second electrode of the first transistor is connected to the fourth node;

a gate of the second transistor is connected to the first node, a first electrode of the second transistor is connected to one terminal of the capacitor, and a second electrode of the second transistor is connected to the second node, and another terminal of the capacitor is connected to the first node;

one terminal of the fifth switch is connected to the first node, and another terminal of the fifth switch is connected to the second node;

a first input terminal of the comparator is connected to the first node, a second input terminal of the comparator is connected to the second node, and an output terminal of the comparator is connected to the control portion;

a first input terminal of the second amplifier is connected to the first node, a second input terminal of the second amplifier is connected to the second node, and an output terminal of the second amplifier is connected to the control portion;

the control portion is further connected to the calibration portion and the storage portion respectively, and the calibration portion is further connected to one terminal of the digital-to-analog converter;

another terminal of the digital-to-analog converter is connected to one terminal of the sixth switch; and

another terminal of the sixth switch is connected to the first input terminal of the first amplifier, and the output terminal of the first amplifier is further connected to the data signal terminal of the pixel circuit.

13. An external compensating method, applied to an external compensation circuit, wherein the external compensation circuit comprises:

a regulation sub-circuit and a compensation sub-circuit;

wherein the regulation sub-circuit is connected to a reference current source, a current detection terminal of a pixel circuit, a first node and a second node respectively; and

the compensation sub-circuit is connected to the first node, the second node, and a data signal terminal of the pixel circuit respectively;

the method comprising;

a reset phase, in which the regulation sub-circuit collects a reference current provided by the reference current source, and regulates a potential at the first node and a potential at a second node according to the reference current; and

a detecting phase, in which the regulation sub-circuit collects a driving current loaded to a light-emitting unit by the pixel circuit and regulates the potential at the second node according to the driving current, and the compensation sub-circuit calibrates a data signal to be input to the pixel circuit according to a potential difference between the first node and the second node, and inputs a calibrated data signal to the pixel circuit;

wherein the regulation sub-circuit comprises;

a current amplifying portion and a potential regulating portion;

wherein

the current amplifying portion is connected to the reference current source, the current detection terminal of the pixel circuit, a third node and a fourth node respectively, and configured to amplify a collected current, and input the current that is amplified to the potential regulating portion through the third node and the fourth node, wherein the current is the reference current or the driving current; and

the potential regulating portion is connected to the first node, the second node, the third node and the fourth node respectively, and configured to regulate the potential at the first node and the potential at the second node according to the reference current that is amplified, and regulate the potential at the second node according to the driving current that is amplified.

14. The method according to claim 13, wherein the regulation sub-circuit comprises:

a first amplifier, a first resistance, a second resistance, a first switch, a second switch, a third switch, a fourth switch, a first transistor, a second transistor, a capacitor, and a fifth switch;

wherein

in the reset phase, the first switch is switched off, the second switch, the third switch, and the fifth switch are switched on, and a first terminal and a second terminal of the fourth switch are coupled; and

in the detecting phase, the first switch and the fifth switch are switched off, the second switch and the third switch are switched on, and the first terminal and a third terminal of the fourth switch are coupled.

15. The method according to claim 14, wherein an output terminal of the first amplifier is further connected to the data signal terminal of the pixel circuit;

the external compensation circuit further comprises;

a digital-to-analog converting sub-circuit that comprises a digital-to-analog converter and a sixth switch, and the digital-to-analog converter is connected to a first input terminal of the first amplifier through the sixth switch;

the method further comprises;

a light-emitting phase;

wherein, in the reset phase and the detecting phase, the sixth switch is opened; and

in the light-emitting phase, the first switch and the sixth switch are switched on, the second switch, the third switch and the fifth switch are switched off, and the digital-to-analog converter inputs the calibrated data signal received to the data signal terminal of the pixel circuit through the sixth switch and the first amplifier, to drive the light-emitting unit connected to the pixel circuit to emit light.

16. The method according to claim 13, wherein the external compensation circuit further comprises:

a comparison sub-circuit and an amplification sub-circuit;

wherein

in the detecting phase, the comparison sub-circuit compares the potential at the first node with the potential at the second node, and inputs a comparison result to the compensation sub-circuit;

the amplification sub-circuit amplifies the potential difference and input amplified potential difference to the compensation sub-circuit; and

the compensation sub-circuit calibrates, when the potential at the first node is determined to be not equal to the potential at the second node according to the comparison result, the data signal to be input to the pixel circuit according to the potential difference between the first node and the second node.

17. A display device, comprising:

a pixel circuit and an external compensation circuit connected to the pixel circuit, wherein the external compensation circuit comprises;

a regulation sub-circuit and a compensation sub-circuit;

wherein

the regulation sub-circuit is connected to a reference current source, a current detection terminal of the pixel circuit, a first node and a second node respectively, and configured to regulate a potential at the first node and a potential at the second node according to a reference current provided by the reference current source, and configured to regulate the potential at the second node according to a collected driving current loaded to the light-emitting unit by the pixel circuit;

the compensation sub-circuit is connected to the first node, the second node, and a data signal terminal of the pixel circuit respectively, and configured to calibrate a data signal to be input to the pixel circuit according to a potential difference between the first node and the second node, and input a calibrated data signal to the pixel circuit; and

the regulation sub-circuit comprises;

a current amplifying portion and a potential regulating portion;

wherein

the current amplifying portion is connected to the reference current source, the current detection terminal of the pixel circuit, a third node and a fourth node respectively, and configured to amplify a collected current, and input the current that is amplified to the potential regulating portion through the third node and the fourth node, wherein the current is the reference current or the driving current; and

the potential regulating portion is connected to the first node, the second node, the third node and the fourth node respectively, and configured to regulate the potential at the first node and the potential at the second node according to the reference current that is amplified, and regulate the potential at the second node according to the driving current that is amplified.

18. The display device according to claim 17, wherein the pixel circuit comprises:

a first switching transistor, a second switching transistor, a driving transistor, and a storage capacitor;

wherein

a gate of the first switching transistor is connected to a first switching signal terminal, a first electrode of the first switching transistor, as a data signal terminal, is connected to the compensation sub-circuit, and a second electrode of the first switching transistor is connected to a gate of the driving transistor;

a first electrode of the driving transistor is connected to a ground terminal, a second electrode of the driving transistor is connected to one terminal of the storage capacitor, another terminal of the storage capacitor is connected to a light-emitting unit; and

a gate of the second switching transistor is connected to a second switching signal terminal, a first electrode of the second switching transistor is connected to one terminal of the storage capacitor, and a second electrode of the second switching transistor, as a current detection terminal, is connected to a third terminal of a fourth switch in the regulation sub-circuit.

19. The display device according to claim 17, wherein the compensation sub-circuit is connected to a first input terminal of a first amplifier in the regulation sub-circuit, and an output terminal of the first amplifier is further connected to the data signal terminal.

20. The display device according to claim 17, wherein the current amplifying portion comprises:

a first amplifier, a first resistance, a second resistance, a first switch, a second switch, a third switch, and a fourth switch;

wherein

a first input terminal of the first amplifier is connected to one terminal of the third switch, a second input terminal of the first amplifier is connected to a fifth node, and an output terminal of the first amplifier is connected to the third node, wherein another terminal of the third switch is connected to a direct current power source terminal;

one terminal of the first resistance is connected to one terminal of the second switch, and another terminal of the first resistance is connected to the fourth node, wherein another terminal of the second switch is connected to the fifth node;

one terminal of the second resistance is connected to the fourth node, and another terminal of the second resistance is connected to the direct current power source terminal;

one terminal of the first switch is connected to the fifth node, and another terminal of the first switch is connected to the third node; and

a first terminal of the fourth switch is connected to the fifth node, a second node of the fourth switch is connected to the reference current source, and a third terminal of the fourth switch is connected to the current detection terminal of the pixel circuit.