Gate contact over active enabled by alternative spacer scheme and claw-shaped cap

• US 10,943,990 B2
• Filed: 10/25/2018
• Issued: 03/09/2021
• Est. Priority Date: 10/25/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Greene, Andrew, Chan, Victor W. C., Muthinti, Gangadhara Raja, Basker, Veeraraghavan, Wang, Junli, Choi, Kisik, Fan, Su Chen
• Primary Examiner(s): Whalen, Daniel
• Application Number:
  US16/171,081
• Publication Number:
  US 20200135886A1
• Time in Patent Office: 866 Days
• CPC Class Codes: H01L 21/28132 conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

Gate contact over active layout designs are provided. In one aspect, a method for forming a gate contact over active device includes: forming a device including metal gates over an active area of a wafer, and source/drains on opposite sides of the metal gates offset by gate spacers; recessing the metal gates/gate spacers; forming etch-selective spacers on top of the recessed gate spacers; forming gate caps on top of the recessed metal gates; forming source/drain contacts on the source/drains; forming source/drain caps on top of the source/drain contacts, wherein the etch-selective spacers provide etch selectivity to the gate caps and source/drain caps; and forming a metal gate contact that extends through one of the gate caps, wherein the etch-selective spacers prevent gate-to-source drain shorting by the metal gate contact. Alternate etch-selective configurations are also provided including a claw-shaped source/drain cap design. A gate contact over active device is also provided.

Claims

1. A method for forming a gate contact over active device, the method comprising the steps of:

forming a device comprising metal gates over an active area of a wafer, and sources and drains on opposite sides of the gates offset from the gates by gate spacers;

recessing the metal gates and the gate spacers;

forming etch-selective spacers on top of the recessed gate spacers;

forming gate caps on top of the recessed metal gates in between the etch-selective spacers;

forming source and drain contacts on the sources and drains;

forming source and drain caps on top of the source and drain contacts, wherein the etch-selective spacers are present between the gate caps and the source and drain caps and provide etch selectivity to both the gate caps and the source and drain caps; and

forming a metal gate contact that extends through a given one of the gate caps, wherein the etch-selective spacers prevent gate-to-source drain shorting by the metal gate contact.

2. The method of claim 1, further comprising the steps of:

covering the sources and drains with an interlayer dielectric (ILD);

recessing the metal gates and the gate spacers selective to the ILD;

depositing a conformal liner on the recessed metal gates, the recessed gate spacers, and the ILD; and

etching back the liner to form the etch-selective spacers on top of the recessed gate spacers.

3. The method of claim 2, further comprising the step of:

removing the ILD prior to forming the source and drain contacts on the sources and drains.

4. The method of claim 1, further comprising the step of:

forming a metal source and drain contact that extends through a given one of the source and drain caps, wherein the etch-selective spacers prevent gate-to-source drain shorting by the metal source and drain contact.

5. The method of claim 1, further comprising the step of:

forming a metal source and drain contact that extends through another given one of the gate caps and a given one of the source and drain caps and is present over a given one of the etch-selective spacers.

6. The method of claim 1, wherein the gate caps comprise a material selected from the group consisting of:

silicon nitride (SiN), silicon oxycarbonitride (SiOCN), and combinations thereof.

7. The method of claim 1, wherein the etch-selective spacers comprise a material selected from the group consisting of:

silicon carbide (SiC), aluminum oxide (AlOx), hafnium oxide (HfOx), aluminum nitride (AlN), and combinations thereof.

8. The method of claim 7, wherein the source and drain caps comprise a different material from etch-selective spacers selected from the group consisting of:

SiC, AlOx, HfOx, AlN, and combinations thereof.

9. The method of claim 8, wherein the source and drain caps comprise a higher-κ

material than the etch-selective spacers.

10. The method of claim 9, wherein the etch-selective spacers comprise AlOx, and wherein the source and drain caps comprise HfOx.

11. The method of claim 1, wherein the etch-selective spacers have a height H_SPACER, wherein the source and drain caps have a thickness T_CAP, and wherein H_SPACER≥

T_CAP.

12. The method of claim 1, further comprising the steps of:

depositing another ILD onto the gate caps, the source and drain caps and the etch-selective spacers;

patterning a trench in the other ILD that extends through the given gate cap, wherein the etch-selective spacers prevent erosion of the gate spacers during the patterning; and

filling the trench with at least one contact metal to form the metal gate contact.

13. A gate contact over active device, comprising:

metal gates over an active area of a wafer;

sources and drains on opposite sides of the metal gates offset from the metal gates by gate spacers;

gate caps on top of the metal gates;

an etch-selective material directly contacting a top surface of the gate spacers alongside the gate caps which provides etch selectivity to the gate caps;

source and drain contacts on the sources and drains;

source and drain caps on top of the source and drain contacts; and

a metal gate contact that extends through a given one of the gate caps, wherein the etch-selective material prevents gate-to-source drain shorting by the metal gate contact.

14. The gate contact over active device of claim 13, wherein the etch-selective material comprises etch-selective spacers that are present between the gate caps and the source and drain caps, and wherein the etch-selective spacers provide etch selectivity to both the gate caps and the source and drain caps.

15. The gate contact over active device of claim 13, wherein the etch-selective material is a component of the source and drain caps which form claw-shaped caps over the source and drain contacts.