TFT substrate and manufacturing method thereof

• US 10,964,790 B1
• Filed: 09/14/2018
• Issued: 03/30/2021
• Est. Priority Date: 04/27/2018
• Status: Active Grant

• Current Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: Yan, Yuan, Li, Lisheng, Song, Dewei
• Primary Examiner(s): Movva, Amar
• Application Number:
  US16/097,838
• Publication Number:
  US 20210098582A1
• Time in Patent Office: 928 Days
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/76844 Bottomless liners
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78633 with a light shield

Abstract

The present invention teaches a TFT substrate manufacturing method and a TFT substrate. The method configures contact region vias in the source/drain contact regions at two ends of the active layer, provides buffer layer troughs in the buffer layer beneath the contact region vias, and forms undercut structure between the buffer layer troughs and the active layer around the contact region vias, thereby separating the transparent conductive layer at the contact region vias, and extending the source/drain electrodes to contact the source/drain contact regions of the active layer from below through the buffer layer troughs. The present invention therefore prevents the occurrence of Schottky contact barrier resulted from the contact between poly-Si and ITO in the 7-mask process by letting the source/drain electrodes to directly contact and form ohmic contact with the source/drain contact regions of the active layer, thereby enhancing the electronic mobility of TFT devices.

Claims

1. A TFT substrate manufacturing method, comprising

step S1:

providing a substrate, and sequentially forming a buffer layer, an active layer, a gate insulation layer, an interlayer dielectric (ILD) layer, and a planarization (PLN) layer from bottom to top on the substrate, where the active layer comprises source/drain contact regions at two ends, each having a contact region via, and a ditch region in the center of the active layer;

step S2;

conducting exposure and development to the PLN layer to form photoresist vias on the PLN layer above the contact region vias, performing a first etching to the ILD layer, the gate insulation layer, and the buffer layer using the PLN layer as a shielding layer to form insulation layer vias connecting the contact region vias on the ILD layer and the gate insulation layer, and forming buffer layer troughs connecting the contact region vias on the buffer layer;

step S3;

conducting a second etching to the buffer layer to laterally widen the buffer layer troughs, where an undercut structure is formed between the buffer layer troughs and the active layer around the contact region vias; and

step S4;

sequentially forming a transparent conductive layer and a metallic layer on the ILD layer by deposition, where the transparent conductive layer is separated by the contact region vias, and the metallic layer is continuously extended into and fills up the buffer layer troughs, and patterning the transparent conductive layer and the metallic layer to form the source/drain electrodes and touch line from the metallic layer, and the pixel electrodes from the transparent conductive layer, where the source/drain electrodes contact the source/drain contact regions of the active layer from below through the buffer layer troughs.

2. The TFT substrate manufacturing method according to claim 1, further comprising step S5:

forming a passivation layer on the ILD layer covering the transparent conductive layer and the metallic layer, and forming a common electrode layer on the passivation layer by deposition and patterning.

3. The TFT substrate manufacturing method according to claim 1, wherein the transparent conductive layer is made of indium tin oxide (ITO);

the active layer is a low temperature poly-silicon (LTPS) layer; and

step S1 forms a shading layer on the substrate before forming the buffer layer.

4. The TFT substrate manufacturing method according to claim 1, wherein the buffer layer is a combination of a silicon oxide (SiOx) layer and a silicon nitride (SiNx) layer;

the SiOx layer is stacked on the SiNx layer; and

the buffer layer troughs formed in step S2 is in the SiOx layer.

5. The TFT substrate manufacturing method according to claim 4, wherein the SiOx layer in the buffer layer has a refractive index between 1.40 and 1.47.

6. The TFT substrate manufacturing method according to claim 1, wherein step S2 conducts the first etching to the ILD layer, the gate insulation layer, and the buffer layer using dry etching with an etching gas containing carbon tetrafluoride (CF₄).

7. The TFT substrate manufacturing method according to claim 1, wherein step S3 conducts the second etching to the buffer layer using dry etching with an etching gas containing pentafluoroethane (C₂HF₅).

8. The TFT substrate manufacturing method according to claim 1, wherein step S4 comprises:

step S41;

sequentially forming the transparent conductive layer and the metallic layer by deposition, coating a photoresist layer on the metallic layer, and obtaining a photoresist pattern by exposing the photoresist layer using the HTM mask and developing the photoresist layer;

step S42;

conducting a first etching to the transparent conductive layer and the metallic layer using the photoresist pattern as a shielding layer to obtain stacked transparent conductive pattern and metallic pattern, where the metallic pattern includes a target metallic pattern and a to-be-removed metallic pattern, the transparent conductive pattern includes a reserved conductive pattern and a target conductive pattern, beneath and corresponding to the target metallic pattern and the to-be-removed metallic pattern, respectively, the target metallic pattern includes source/drain electrodes and touch line, and the target conductive pattern includes pixel electrode; and

step 43;

removing the photoresist pattern above the to-be-removed metallic pattern using an ashing process, conducting a second etching to the metallic layer to remove the to-be-removed metallic pattern and to expose the target conductive pattern.

9. The TFT substrate, comprising a substrate, a buffer layer on the substrate, an active layer on the buffer layer, a gate insulation layer on the buffer layer covering the active layer, a gate electrode on the gate insulation layer, an ILD layer on the gate insulation layer covering the gate electrode, a transparent conductive layer on the ILD layer, and a metallic layer on the transparent conductive layer, wherein

the active layer comprises source/drain contact regions at two ends, each having a contact region via, and a ditch region in the center of the active layer;

insulation layer vias are configured in the ILD layer and the gate insulation layer connecting the contact region vias, buffer layer troughs are configured on the buffer layer connecting the contact region vias, undercut structure is formed between the buffer layer troughs and the active layer around the contact region vias; and

the transparent conductive layer is separated by the contact region vias, the metallic layer is continuously extended into and fills up the buffer layer troughs, the metallic layer comprises source/drain electrodes and touch line, the source/drain electrodes contact the source/drain contact regions of the active layer from below through the buffer layer troughs.

10. The TFT substrate according to claim 9, further comprising a shading layer between the substrate and the buffer layer, a passivation layer on the ILD layer covering the transparent conductive layer and the metallic layer, and a common electrode layer on the passivation layer, wherein

the transparent conductive layer is made of indium tin oxide (ITO);

and

the active layer is a low temperature poly-silicon (LTPS) layer.