Display panel having electrostatic discharge circuit and display device

• US 10,989,970 B2
• Filed: 05/12/2017
• Issued: 04/27/2021
• Est. Priority Date: 05/09/2017
• Status: Active Grant

• Current Assignee: Chongqing HKC Optoelectronics Technology Co., Ltd. (Shenzhen Huike Investment Holding Co., Ltd.), HKC Corporation Limited (Shenzhen Huike Investment Holding Co., Ltd.)
• Original Assignee: HKC Corporation Limited (Shenzhen Huike Investment Holding Co., Ltd.)
• Inventors: Chen, Yu-Jen
• Primary Examiner(s): De Leon Domenech, Rafael O
• Application Number:
  US16/325,749
• Publication Number:
  US 20190204693A1
• Time in Patent Office: 1,446 Days
• CPC Class Codes: G02F 1/136204 Arrangements to prevent high voltage or static electricity failures
• CPC Class Codes: G02F 2202/22 Antistatic materials or arrangements
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2330/04 Display protection
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 27/0296 involving a specific disposition of the protective devices

Abstract

The present application disclose a display panel and display device, including a substrate, and an electrostatic discharge circuit disposed on the substrate and including a voltage gate high terminal (VGH terminal), a voltage gate low terminal (VGL terminal), an electrostatic input end and a common voltage terminal (VCOM terminal) coupled with components of the display panel; and a first discharge circuit, where an output end of the first discharge circuit is respectively connected to the voltage gate high terminal and the voltage gate low terminal, and a control end and an input end of the first discharge circuit are connected to the electrostatic input end; and a second discharge circuit, where an input end of the second discharge circuit is connected to the electrostatic input end, and an output end of the second discharge circuit is connected to the common voltage terminal.

Claims

1. A display panel, comprising:

a substrate comprise a plurality of pixel regions; and

an electrostatic discharge circuit disposed on the substrate;

wherein the electrostatic discharge circuit comprises a voltage gate high terminal (VGH terminal), a voltage gate low terminal (VGL terminal), an electrostatic input end and a common voltage terminal (VCOM terminal) coupled with components of the display panel;

a first discharge circuit, wherein an output end of the first discharge circuit is connected to the voltage gate high terminal and the voltage gate low terminal respectively, a control end of the first discharge circuit are connected to the electrostatic input end, and an input end of the first discharge circuit are connected to the electrostatic input end; and

a second discharge circuit, wherein an input end of the second discharge circuit is connected to the electrostatic input end, and an output end of the second discharge circuit is connected to the common voltage terminal;

wherein the first discharge circuit comprises a first N-type thin film transistor and a second N-type thin film transistor, a source of the first N-type thin film transistor is connected to the voltage gate high terminal, a gate of the first N-type thin film transistor is connected to a drain of the first N-type thin film transistor, and the gate and the drain of the first N-type thin film transistor are also connected to a source of the second N-type thin film transistor, the source of the second N-type thin film transistor is also connected to the electrostatic input end, a gate of the second N-type thin film transistor is connected to a drain of the second N-type thin film transistor, and the gate and the drain of the second N-type thin film transistor are also connected to the voltage gate low terminal; and

the second discharge circuit comprises a third N-type thin film transistor, a capacitor and a fourth N-type thin film transistor, a source of the third N-type thin film transistor is connected to the gate of the first P-type thin film transistor, a drain of the third N-type thin film transistor is connected to the common voltage terminal, the common voltage terminal is connected to GND, a first end of the capacitor is connected to the electrostatic input end, a second end of the capacitor is connected to a gate of the third N-type thin film transistor, a source of the fourth N-type thin film transistor is connected to the second end of the capacitor, a gate of the fourth N-type thin film transistor is connected to the voltage gate high terminal, a drain of the fourth N-type thin film transistor is connected to the voltage gate low terminal, the display panel comprises a gate integrated circuit, and the voltage gate high terminal and the voltage gate low terminal are respectively connected at a thin film transistor voltage turn-on end and a thin film transistor voltage turn-off end of the gate integrated circuit.

2. A display panel, comprising:

a substrate including a plurality of pixel regions; and

an electrostatic discharge circuit disposed on the substrate;

wherein the electrostatic discharge circuit comprises a voltage gate high terminal, a voltage gate low terminal, an electrostatic input end and a common voltage terminal coupled with components of the display panel; and

a first discharge circuit, wherein an output end of the first discharge circuit is connected to the voltage gate high terminal and the voltage gate low terminal respectively, a control end of the first discharge circuit is connected to the electrostatic input end, and an input end of the first discharge circuit is connected to the electrostatic input end; and

a second discharge circuit, wherein an input end of the second discharge circuit is connected to the electrostatic input end, and an output end of the second discharge circuit is connected to the common voltage terminal.

3. The display panel according to claim 2, wherein the second discharge circuit comprises a first conducting line with one end connected to the common voltage terminal, and the common voltage terminal is connected to GND.

4. The display panel according to claim 2, wherein the second discharge circuit comprises a first conducting line with one end connected to the common voltage terminal, and the common voltage terminal is connected to a common voltage end of the display panel.

5. The display panel according to claim 2, wherein the second discharge circuit comprises a third thin film transistor, an input end of the third thin film transistor is connected to the electrostatic input end, a control end of the third thin film transistor is connected to the electrostatic input end, and an output end of the third thin film transistor is connected to the common voltage terminal.

6. The display panel according to claim 5, wherein the second discharge circuit comprises a capacitor, a first end of the capacitor is connected to the electrostatic input end, and a second end of the capacitor is connected to the control end of the third thin film transistor.

7. The display panel according to claim 6, wherein the second discharge circuit comprises a fourth thin film transistor, an input end of a fourth thin film transistor is connected to the second end of the capacitor, a control end of the fourth thin film transistor is connected to the voltage gate high terminal, an output end of the fourth thin film transistor is connected to the voltage gate low terminal;

or, an input end of a fourth thin film transistor is connected to the second end of the capacitor, a control end of the fourth thin film transistor is connected to the voltage gate low terminal, and an output end of the fourth thin film transistor is connected to the voltage gate high terminal.

8. The display panel according to claim 5, wherein the third thin film transistor and the fourth thin film transistor are P-type Thin film transistors.

9. The display panel according to claim 6, wherein the third the third thin film transistor and the fourth thin film transistor are N-type thin film transistors.

10. The display panel according to claim 2, wherein the first discharge circuit comprises a first N-type thin film transistor and a second N-type thin film transistor, a source of the first N-type thin fin transistor is connected to the voltage gate high terminal, a gate of the first N-type thin film transistor is connected to a drain of the first N-type thin film transistor, and the gate and the drain of the first N-type thin film transistor are also connected to a source of the second N-type thin film transistor, the source of the second N-type thin film transistor is also connected to the electrostatic input end, a gate of the second N-type thin film transistor is connected to a drain of the second N-type thin film transistor, and the gate and the drain of the second N-type thin film transistor are also connected to the voltage gate low terminal;

and

the second discharge circuit comprises a third N-type thin film transistor, a capacitor and a fourth N-type thin film transistor, a source of the third N-type thin film transistor is connected to a gate of the first N-type thin film transistor, a drain of the third N-type thin film transistor is connected to the common voltage terminal, the common voltage terminal is connected to GND, a first end of the capacitor is connected to the electrostatic input end, a second end of the capacitor is connected to a gate of the third N-type thin film transistor, a source of the fourth N-type thin film transistor is connected to the second end of the capacitor, a gate of the fourth N-type thin film transistor is connected to the voltage gate high terminal, and a drain of the fourth N-type thin film transistor is connected to the voltage gate low terminal.

11. The display panel according to claim 2, wherein the first discharge circuit comprises a first P-type thin film transistor and a second P-type thin film transistor, a gate of the first P-type thin film transistor is connected to a drain of the first P-type thin film transistor, and the gate and the drain of the first P-type thin film transistor are also connected to the voltage gate high terminal, a source of the first P-type thin film transistor is connected to the electrostatic input end, a gate of the second P-type thin film transistor is connected to a drain of the second P-type thin film transistor, and the gate and the drain of the second P-type thin film transistor are also connected to the source of the first P-type thin film transistor, and a source of the second P-type thin film transistor is connected to the voltage gate low terminal;

wherein the second discharge circuit comprises a third N-type thin film transistor, a capacitor and a fourth N-type thin film transistor, a source of the third N-type thin film transistor is connected to the gate of the first P-type thin film transistor, a drain of the third N-type thin film transistor is connected to the common voltage terminal, the common voltage terminal is connected to GND, a first end of the capacitor is connected to the electrostatic input end, a second end of the capacitor is connected to a gate of the third N-type thin film transistor, a source of the fourth N-type thin film transistor is connected to the second end of the capacitor, a gate of the fourth N-type thin film transistor is connected to the voltage gate high terminal, and a drain of the fourth N-type thin film transistor is connected to the voltage gate low terminal.

12. The display panel according to claim 2, wherein the first discharge circuit comprises a first P-type thin film transistor and a second P-type thin film transistor, a gate of the first P-type thin film transistor is connected to a drain of the first P-type thin film transistor, and the gate and the drain of the first P-type thin film transistor are also connected to the voltage gate high terminal, a source of the first P-type thin film transistor is connected to the electrostatic input end, a gate of the second P-type thin film transistor is connected to a drain of the second P-type thin film transistor, and the gate and the drain of the second P-type thin film transistor are also connected to the source of the first P-type thin film transistor, and a source of the second P-type thin film transistor is connected to the voltage gate low terminal;

and

the second discharge circuit comprises a third P-type thin film transistor, a capacitor and a fourth P-type thin film transistor, a source of the third P-type thin film transistor is connected to the gate of the second P-type thin film transistor, a drain of the third P-type thin film transistor is connected to the common voltage terminal, the common voltage terminal is connected to GND, a first end of the capacitor is connected to the electrostatic input end, a second end of the capacitor is connected to a gate of the third P-type thin film transistor, a source of the fourth P-type thin film transistor is connected to the second end of the capacitor, a gate of the fourth P-type thin film transistor is connected to the voltage gate low terminal, and a drain of the fourth P-type thin film transistor is connected to the voltage gate high terminal.

13. The display panel according to claim 2, wherein the display panel comprises a gate integrated circuit, and the voltage gate high terminal and the voltage gate low terminal are respectively connected at a thin film transistor voltage turn-on end and a thin film transistor voltage turn-off end of the gate integrated circuit.

14. A display device, comprising a display panel, comprising:

a substrate including a plurality of pixel regions; and

an electrostatic discharge circuit disposed on the substrate;

wherein the electrostatic discharge circuit comprises a voltage gate high terminal, a voltage gate low terminal, an electrostatic input end and a common voltage terminal coupled with components of the display panel; and

a first discharge circuit, wherein an output end of the first discharge circuit is connected to the voltage gate high terminal and the voltage gate low terminal respectively, a control end of the first discharge circuit is connected to the electrostatic input end, and an input end of the first discharge circuit is connected to the electrostatic input end; and

a second discharge circuit, wherein an input end of the second discharge circuit is connected to the electrostatic input end, and an output end of the second discharge circuit is connected to the common voltage terminal.

15. The display device according to claim 14, wherein the second discharge circuit comprises a first conducting line with one end connected to the common voltage terminal, and the common voltage terminal is connected to GND.

16. The display device according to claim 14, wherein the second discharge circuit comprises a first conducting line with one end connected to the common voltage terminal, and the common voltage terminal is connected to a common voltage end of the display panel.

17. The display device according to claim 14, wherein the second discharge circuit comprises a third thin film transistor, an input end of the third thin film transistor is connected to the electrostatic input end, a control end of the third thin film transistor is connected to the electrostatic input end, and an output end of the third thin film transistor is connected to the common voltage terminal.

18. The display device according to claim 17, wherein the second discharge circuit comprises a capacitor, a first end of the capacitor is connected to the electrostatic input end, and a second end of the capacitor is connected to the control end of the third thin film transistor.

19. The display device according to claim 18, wherein the second discharge circuit comprises a fourth thin film transistor, an input end of a fourth thin film transistor is connected to the second end of the capacitor, a control end of the fourth thin film transistor is connected to the voltage gate high terminal, an output end of the fourth thin film transistor is connected to the voltage gate low terminal, an input end of a fourth thin film transistor is connected to the second end of the capacitor.

20. The display device according to claim 18, wherein the second discharge circuit comprises a fourth thin film transistor, an input end of a fourth thin film transistor is connected to the second end of the capacitor, a control end of the fourth thin film transistor is connected to the voltage gate low terminal, and an output end of the fourth thin film transistor is connected to the voltage gate high terminal.