Hybrid processor

• US 10,996,959 B2
• Filed: 01/07/2016
• Issued: 05/04/2021
• Est. Priority Date: 01/08/2015
• Status: Active Grant

• Current Assignee: TECHNION RESEARCH AND DEVELOPMENT FOUNDATION, LTD.
• Original Assignee: TECHNION RESEARCH AND DEVELOPMENT FOUNDATION, LTD.
• Inventors: Morad, Amir, Yavits, Leonid, Kvatinsky, Shahar, Ginosar, Ran
• Primary Examiner(s): Giardino, Jr., Mark A
• Application Number:
  US14/989,880
• Publication Number:
  US 20160224465A1
• Time in Patent Office: 1,944 Days
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox
• CPC Class Codes: G06F 15/7825 Globally asynchronous, locally synchronous, e.g. network on chip
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A hybrid computer that comprises a sequential processor, a single instruction massively parallel (SIMD) processor, and shared memory module that is shared between the sequential processor and the SIMD processor.

Claims

1. A hybrid computer that comprises a sequential processor, a single instruction massively parallel (SIMD) processor, and shared memory module that is configured to store shared data that is shared between the sequential processor and the SIMD processor;

wherein the sequential processor is configured to access data in the shared memory module during an execution of sequential segments of a workload; and

wherein the SIMD processor is configured to access the data in the shared memory module during an execution of parallelizable segments of the workload;

wherein the SIMD processor comprises a sequencer and processing units that comprise register files, wherein the sequencer is configured to control data transfers from the shared memory to the SIMD by broadcasting a conditional micro-instruction to the processing units, wherein an execution of at least one conditional micro-instruction by a processing unit is conditioned by a single bit register and wherein the conditional micro-instruction comprises a multi-bit field that is indicative of a type, out of multiple types, of the conditional micro-instruction.

2. The hybrid computer according to claim 1 wherein the shared memory module is configured to support row access to rows of the shared memory module and to support column access to columns of the shared memory module;

and wherein the SIMD processor is arranged to perform a row access of the shared memory module while the sequential processor is arranged to perform a column access of the shared memory module.

3. The hybrid computer according to claim 1 wherein the SIMD processor and the sequential processor are arranged to concurrently access the shared memory module.

4. The hybrid computer according to claim 1 wherein the SIMD processor and the sequential processor are arranged to access the shared memory module in an interleaved manner without a timing overlap, wherein an access of the shared memory module by the SIMD processor and an access of the sequential processor to the shared memory modules are separated into distinct operations.

5. The hybrid computer according to claim 1 wherein the shared memory module comprises at least one SIMD memory region that is writable only by the SIMD processor and at least one sequential processor memory region that is writable only by the sequential processor.

6. The hybrid computer according to claim 1 wherein the shared memory module comprises at least one SIMD memory region that is writable only by the SIMD processor.

7. The hybrid computer according to claim 1 wherein the shared memory module comprises at least one SIMD memory region that is writable only by the SIMD processor;

wherein the sequential processor is configured to read content stored in the SIMD memory region.

8. The hybrid computer according to claim 1 wherein the shared memory module comprises at least one SIMD memory region that is writable only by the SIMD processor;

wherein the sequential processor is prevented from reading content stored in the SIMD memory region.

9. The hybrid computer according to claim 1 wherein the shared memory module comprises shared memory cells that are shared by the SIMD processor and by the sequential processor, and non-shared memory cells that are accessed only by one of the SIMD processor and the sequential processor;

wherein the shared memory cells comprises more transistors than the non-shared memory cells.

10. The hybrid computer according to claim 1 wherein the shared memory module comprises shared memory cells that are shared by the SIMD processor and by the sequential processor, and non-shared memory cells that are accessed only by one of the SIMD processor and the sequential processor;

wherein at least some shared memory cells are coupled to at least four control lines.

11. The hybrid computer according to claim 1 wherein the shared memory module comprises at least one sequential processor memory region that is writable only by the sequential processor;

wherein the SIMD processor is configured to read content stored in the sequential processor memory region.

12. The hybrid computer according to claim 1 wherein the sequential processor is configured to control an access of the SIMD processor to the shared memory module.

13. The hybrid computer according to claim 1 wherein the SIMD processor comprises multiple processing units that are configured to operate in parallel to each other.

14. The hybrid computer according to claim 1 wherein the SIMD processor comprises multiple one bit processing units.

15. The hybrid computer according to claim 1 wherein the SIMD processor comprises multiple multi-bit processing units.

16. The hybrid computer according to claim 1 wherein the sequencer is configured to issue commands to at least some of the multiple processing units, an interconnect and a network on chip (NOC) unit.

17. The hybrid computer according to claim 1 wherein the sequencer is configured to issue commands to at least some of the multiple processing units, a reduction tree and a network on chip (NOC) unit.

18. The hybrid computer according to claim 1 wherein the SIMD processor comprises multiple processing units and a reduction tree, wherein the reduction tree comprises a group of adders that are coupled to each other and to outputs of the multiple processing units.

19. The hybrid computer according to claim 1 wherein the SIMD processor comprises multiple processing units, each processing unit comprises an adder, multiple registers, and a function generator.

20. The hybrid computer according to claim 1 wherein the SIMD processor comprises multiple one bit processing units, each one bit processing unit comprises a one bit adder, multiple one bit registers, and a one bit function generator.

21. The hybrid computer according to claim 1 wherein the SIMD processor comprises a first number (N1) of processing units, wherein the SIMD processor is arranged to perform arithmetic operations on vectors that have a second number (N2) of elements by performing multiple iterations of N1 length arithmetic operations;

wherein N2 exceeds N1.

22. The hybrid computer according to claim 1 wherein the SIMD processor comprises a first number (N1) of processing units, wherein the SIMD processor is arranged to perform a search for a key within a vector of a second number (N2) of elements by performing multiple compare operations with different segments of the vector wherein a length of the key does not exceed N1 and wherein N2 exceeds N1.

23. The hybrid computer according to claim 1 comprising a group of SIMD processors, wherein the shared memory module is virtually segmented to a group of shared memory segments;

wherein each SIMD processor of the group of SIMD processors is arranged to access a single shared memory segment of the group of shared memory segments.

24. The hybrid computer according to claim 1 comprising a group of SIMD processors, wherein the shared memory module is virtually segmented to a group of shared memory segments;

wherein the sequential processor is arranged to access to each shared memory segment of the group of shared memory segments;

wherein each SIMD processor of the group of SIMD processors is arranged to access a single shared memory segment of the group of shared memory segments.

25. The hybrid computer according to claim 1 wherein the shared memory module comprises memory cells that comprise memristive devices.

26. The hybrid computer according to claim 1 wherein the shared memory module comprises shared memory cells that are accessible to both the SIMD processor and to the sequential processor;

wherein the shared memory cells comprise memristive devices and diodes.

27. The hybrid computer according to claim 1 wherein the shared memory module comprises shared memory cells that are accessible to both the SIMD processor and to the sequential processor;

wherein the shared memory cells comprise memristive devices;

wherein one end of each shared memory cell is coupled to SIMD processor access circuits and wherein another end of each shared memory cell is coupled to sequential processor access circuits.

28. The hybrid computer according to claim 1 wherein the SIMD processor comprises multiple processing units that comprise memristive devices.

29. The hybrid computer according to claim 1 wherein the shared memory module and the SIMD processor are integrated and comprise memristive devices that are configured to operate as memory cells and to perform arithmetic operations.

30. The hybrid computer according to claim 1 wherein the shared memory module comprises memory cells that comprise multiple bit memristive devices.

31. The hybrid computer according to claim 1 wherein SIMD processor and the shared memory module are integrated and comprise combined memory and computation cells;

wherein each memory and computation cell comprises a memristive device;

wherein the hybrid computer is configured to perform an addition operation of first and second operands, using a certain memristive device of a certain combined memory and computation cell, by storing in the certain memristive device a value that corresponds to the second operand and feeding the certain memristive devices with one or more programming pulses that correspond to the first operand in a direction that decreases a resistivity of the certain memristive device.

32. The hybrid computer according to claim 1 wherein SIMD processor and the shared memory module are integrated and comprise combined memory and computation cells;

wherein each memory and computation cell comprises a memristive device;

wherein the hybrid computer is configured to perform a subtraction operation of first and second operands, using a certain memristive device of a certain combined memory and computation cell, by storing in the certain memristive device a value that corresponds to the second operand and feeding the certain memristive devices with one or more programming pulses that correspond to the first operand in a direction that increases a resistivity of the certain memristive device.

33. The hybrid computer according to claim 1 wherein SIMD processor and the shared memory module are integrated and comprise combined memory and computation cells;

wherein each memory and computation cell comprises a memristive device;

wherein the hybrid computer is configured to perform an addition operation of first and second operands, using a certain memristive device of a certain combined memory and computation cell, by storing in the certain memristive device a value that corresponds to the second operand and feeding the certain memristive devices with one or more programming pulses that correspond to the first operand in a direction that decreases a resistivity of the certain memristive device;

wherein the hybrid computer is configured to perform a subtraction operation of the first and second operands, using the certain memristive device, by storing in the certain memristive device the value that corresponds to the second operand and feeding the certain memristive devices with one or more programming pulses that correspond to the first operand in a direction that increases the resistivity of the certain memristive device;

wherein the hybrid computer is configured to perform long multiplications and long divisions by repeating subtraction and addition operations.

34. The hybrid computer according to claim 1 wherein SIMD processor and the shared memory module are integrated and comprise combined memory and computation cells;

wherein each memory and computation cell comprises only a single memristive device;

wherein the hybrid computer is configured to perform an addition operation of first and second operands, using a certain memristive device of a certain combined memory and computation cell, by storing in the certain memristive device a value that corresponds to the second operand and feeding the certain memristive devices with one or more programming pulses that correspond to the first operand in a direction that decreases a resistivity of the certain memristive device;

wherein the hybrid computer is configured to perform a subtraction operation of the first and second operands, using the certain memristive device, by storing in the certain memristive device the value that corresponds to the second operand and feeding the certain memristive devices with one or more programming pulses that correspond to the first operand in a direction that increases the resistivity of the certain memristive device.

35. A hybrid computer that comprises a sequential processor, a single instruction massively parallel (SIMD) processor, and shared memory module that is configured to store shared data that is shared between the sequential processor and the SIMD processor;

wherein the sequential processor is configured to access data in the shared memory module during an execution of sequential segments of a workload; and

wherein the SIMD processor is configured to access the data in the shared memory module during an execution of parallelizable segments of the workload, wherein the hybrid computer is configured to perform dense matrix multiplication of a first matrix (A) by a second matrix (B), wherein during the performing of the dense matrix multiplication the sequential processor is configured to match row elements of the second matrix with corresponding column elements of the first matrix;

wherein the match is executed as a sequence of associative operations; and

wherein the SIMD processor is configured to multiply pairs of matched row elements of the second matrix by the corresponding column elements of the first matrix to provide singleton products and to add single products together.

36. A hybrid computer that comprises a sequential processor, a single instruction massively parallel (SMD) processor, and shared memory module that is configured to store shared data that is shared between the sequential processor and the SMD processor;

wherein he sequential processor is configured to access data in the shared memory module during an execution of sequential segments of a workload; and

wherein the SMD processor is configured to access the data in the shared memory module during an execution of parallelizable segments of the workload, wherein the hybrid computer is configured to perform sparse matrix multiplication of a first matrix (A) by a second matrix (B), wherein during the performing of the sparse matrix multiplication the sequential processor is configured to match row elements of the second matrix with corresponding non-zero column elements of the first matrix;

wherein the match is executed as a sequence of associative operations; and

wherein the SMD processor is configured to multiply pairs of matched row elements of the second matrix by the corresponding column elements of nonzero columns of the first matrix to provide singleton products and to add single products together.