Method for programming a memory system

• US 10,998,062 B2
• Filed: 01/15/2019
• Issued: 05/04/2021
• Est. Priority Date: 12/07/2018
• Status: Active Grant

• Current Assignee: Yangtze Memory Technologies Co., Ltd. (Yangtze River Storage Technology Holdings Co. , Ltd.)
• Original Assignee: Yangtze Memory Technologies Co., Ltd. (Yangtze River Storage Technology Holdings Co. , Ltd.)
• Inventors: Li, Haibo, Tang, Qiang
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US16/248,719
• Publication Number:
  US 20200185046A1
• Time in Patent Office: 840 Days
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification

Abstract

A memory system includes a plurality of blocks of memory blocks, each including a plurality of memory cells. The method for programming the memory system includes during a program process, performing a first program operation to program a first memory block, waiting for a delay time after the first program operation is completed, after waiting for the delay time, performing an all-level threshold voltage test to determine if threshold voltages of the first memory block are greater than corresponding threshold voltages, and performing a second program operation to program the first memory block according to a result of the all-level threshold voltage test.

Claims

1. A method for programming a memory system, the memory system comprising a plurality of memory blocks, each comprising a plurality of memory cells, the method comprising:

performing a background media scan to determine a data valid ratio of a second memory block that has been programmed previously;

when the data valid ratio of the second memory block is determined to be smaller than a threshold value;

copying valid data stored in the second memory block;

selecting a first memory block of the plurality of memory blocks that has not been programmed; and

initiating a program process; and

during the program process;

performing a first program operation to program the first memory block;

waiting for a delay time after the first program operation is completed;

after waiting for the delay time, performing an all-level threshold voltage test to determine if threshold voltages of memory cells in the first memory block are greater than corresponding threshold voltages; and

performing a second program operation to program the first memory block according to a result of the all-level threshold voltage test.

2. The method of claim 1, wherein performing the first program operation to program the first memory block of the plurality blocks of memory cell comprises programming the valid data stored in the second memory block to the first memory block.

3. The method of claim 1, further comprising performing an erase operation to erase the second memory block.

4. The method of claim 1, wherein the background media scan is performed periodically.

5. The method of claim 1, wherein performing the second program operation to program the first memory block according to the result of the all-level threshold voltage test comprises:

during the second program operation, inhibiting memory cells in the first memory block that pass the all-level threshold voltage test.

6. The method of claim 1, wherein the program process is initiated when a length of a programming time is not critical to the memory system.

7. The method of claim 1, wherein the first memory block are coupled to different word lines, and memory cell coupled to a same word line in the first memory block are programmed simultaneously during the first program operation and the second program operation.

8. The method of claim 1, wherein the memory system is a NAND flash memory system.

9. A method for programming a memory system, the memory system comprising a plurality of memory blocks, each comprising a plurality of memory cells, the method comprising:

during a program process;

performing a first program operation to program a first memory block of the plurality of memory blocks, the first program operation comprising;

generating a first program voltage pulse to program the first memory block;

performing a first-level threshold voltage test to determine if threshold voltages of the first memory block are greater than a first threshold voltage;

generating a second program voltage pulse to program the first memory block according to a result of the first-level threshold voltage test;

performing a second-level threshold voltage test to determine if the threshold voltages of the first memory block are greater than a second threshold voltage greater than the first threshold voltage; and

generating a third program voltage pulse to program the first memory block according to a result of the second-level threshold voltage test;

waiting for a delay time after the first program operation is completed;

after waiting for the delay time, performing an all-level threshold voltage test to determine if threshold voltages of memory cells in the first memory block are greater than corresponding threshold voltages; and

performing a second program operation to program the first memory block according to a result of the all-level threshold voltage test.

10. The method of claim 9, wherein the third program voltage pulse is greater than the second program voltage pulse, and the second program voltage pulse is greater than the first program voltage pulse.

11. A method for programming a memory system, the memory system comprising a plurality of memory blocks, each comprising a plurality of memory cells, the method comprising:

during a program process;

performing a first program operation to program a first memory block of the plurality of memory blocks;

waiting for a delay time after the first program operation is completed;

after waiting for the delay time, performing an all-level threshold voltage test to determine if threshold voltages of memory cells in the first memory block are greater than corresponding threshold voltages; and

performing a second program operation to program the first memory block according to a result of the all-level threshold voltage test, the second program operation comprising;

generating a first program voltage pulse to program the first memory block;

performing a first-level threshold voltage test to determine if threshold voltages of the first memory block are greater than a first threshold voltage;

generating a second program voltage pulse to program the first memory block according to a result of the first-level threshold voltage test;

performing a second-level threshold voltage test to determine if the threshold voltages of the first memory block are greater than a second threshold voltage greater than the first threshold voltage; and

generating a third program voltage pulse greater than the second program voltage pulse to program the first memory block according to a result of the second-level threshold voltage test.

12. The method of claim 11, wherein the third program voltage pulse is greater than the second program voltage pulse, and the second program voltage pulse is greater than the first program voltage pulse.