Mechanism to accelerate graphics workloads in a multi-core computing architecture

• US 11,010,858 B2
• Filed: 01/23/2019
• Issued: 05/18/2021
• Est. Priority Date: 08/05/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Benthin, Carsten, Woop, Sven, Wald, Ingo
• Primary Examiner(s): Hsu, Joni
• Application Number:
  US16/255,721
• Publication Number:
  US 20200134776A1
• Time in Patent Office: 846 Days
• Field of Search: None
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 13/1652 in a multiprocessor architecture interprocessor communication using common memory G06F15/167
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: G06F 9/505 considering the load
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 2200/28 involving image processing hardware
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.

Claims

1. An apparatus comprising:

a plurality of processor cores, including;

a first processor core, wherein the first processor core is a general-purpose processor core; and

a second processor core, wherein the second processor core is a graphics processor core; and

a first field programmable gate array (FPGA) coupled to the first processor core to accelerate execution of workloads processed at the first processor core, wherein the first FPGA provides a first set of independent threads to enable latency hiding; and

a second FPGA coupled to the second processor core to accelerate execution of workloads processed at the second processor core, wherein the second FPGA provides a second set of independent threads to enable latency hiding.

2. The apparatus of claim 1, further comprising a first processor device including the first processor core.

3. The apparatus of claim 2, further comprising a second processor device including the second processor core.

4. The apparatus of claim 3, wherein the first processor core selects a first workload to be accelerated at the first FPGA and the second processor core selects a second workload to be accelerated at the second FPGA.

5. The apparatus of claim 3, wherein logic gates of the first FPGA are programmed to execute a first type of workload, logic gates of the second FPGA are programmed to execute a second type of workload, and the logic gates of the first FPGA and the second FPGA are reprogrammable during the lifetimes of their respective workloads.

6. The apparatus of claim 3, wherein the first processor core comprises a first controller to control execution of the first FPGA, and the second processor core comprises a second controller to control execution of the second FPGA.

7. The apparatus of claim 6, wherein the first controller and the second controller are to control execution of the first FPGA and the second FPGA via memory-mapped I/O (MMIO) regions.

8. The apparatus of claim 7, wherein the first controller and the second controller are to control execution of the first FPGA and the second FPGA via dedicated processor instructions.

9. The apparatus of claim 8, further comprising:

a third processor core of the first processing device, the third processor core coupled to the first FPGA; and

a first cache memory device coupled to the first processor core, third processor core, and the first FPGA.

10. The apparatus of claim 9, wherein the first FPGA is an independent agent to the first cache memory device and the first cache memory device is shared by the first processor core, the third processor core, and the first FPGA.

11. The apparatus of claim 10, wherein the first FPGA is to accelerate execution of workloads processed at the first processor core and the third processor core.

12. The apparatus of claim 10, wherein the first processor device is a central processing unit and additionally includes at least the first FPGA and the second processor device is a graphics processing unit and additionally includes at least the second FPGA.

13. The apparatus of claim 12, further comprising:

a first memory device coupled to the first processor core, the third processor core, and the first FPGA via the first cache memory device; and

a second memory device coupled to the second processor core and the second FPGA.

14. The apparatus of claim 13, further comprising:

a fourth processor core coupled to the second FPGA and the second memory device, wherein the second FPGA accelerates execution of workloads processed at the second processor core and the fourth processor core.

15. A data processing system comprising:

a peripheral bus interconnect; and

a plurality of processor cores coupled with the peripheral bus interconnect, including;

a first processor core, wherein the first processor core is a general purpose processor core;

a second processor core, wherein the second processor core is a graphics processor core; and

a first field programmable gate array (FPGA) coupled to the first processor core to accelerate execution of workloads processed at the first processor core, wherein the first FPGA provides a first set of independent threads to enable latency hiding;

a first cache memory device coupled to the first processor core and the first FPGA;

a second FPGA coupled to the second processor core to accelerate execution of workloads processed at the second processor core, wherein the second FPGA provides a second set of independent threads to enable latency hiding; and

a second cache memory device coupled to the second processor core and the second FPGA.

16. The data processing system of claim 15, further comprising:

a central processing unit including the first processor core, the first FPGA, and the first cache memory device; and

a graphics processing unit including the second processor core, the second FPGA, and the second cache memory device, wherein the first processor core is configured to select a first workload to be accelerated at the first FPGA and the second processor core is configured to select a second workload to be accelerated at the second FPGA.

17. The data processing system of claim 16, wherein logic gates of the first FPGA are programmed to execute a first type of workload, logic gates of the second FPGA are programmed to execute a second type of workload, and the logic gates of the first FPGA and the second FPGA are reprogrammable during the lifetimes of their respective workloads.

18. The data processing system of claim 17, wherein the first processor core comprises a first controller to control execution of the first FPGA, and the second processor core comprises a second controller to control execution of the second FPGA.

19. The data processing system of claim 15, further comprising a third processor core coupled to the first FPGA and the first cache memory device, wherein the first FPGA accelerates execution of workloads processed at the first processor core and the third processor core.