Nonvolatile memory devices

• US 11,017,838 B2
• Filed: 08/12/2020
• Issued: 05/25/2021
• Est. Priority Date: 08/04/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kang, Hee-Woong, Kwak, Dong-Hun, Seo, Jun-Ho, Lee, Hee-Won
• Primary Examiner(s): Tran, Michael T
• Application Number:
  US16/991,693
• Publication Number:
  US 20200372945A1
• Time in Patent Office: 286 Days
• Field of Search: 36518909, 365226, 36518524
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4082 Address Buffers; level conversion circuits
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2207/2209 Concurrent read and write for multi-port memory G11C7/1075
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/12 : Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.

Claims

1. A nonvolatile memory device comprising:

a memory cell array including a plurality of mats, each of the plurality of mats including a plurality of cell strings, wherein;

a first cell string of a first mat of the plurality of mats is connected to a plurality of first word-lines, a first bit-line and a first string selection line,

a second cell string of a second mat of the plurality of mats is connected to a plurality of second word-lines, a second bit-line and a second string selection line,

the first and second cell strings are located perpendicular to a substrate respectively, and

each of the first and second cell strings includes at least one ground selection transistor, a plurality of memory cells, and at least one string selection transistor coupled in series with each other; and

a row decoder connected to the plurality of first and second word-lines and the first and second string selection lines, and configured to apply corresponding word-line voltages to the plurality of first and second word-lines,

wherein the row decoder is configured to;

apply a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time when a first operation of the nonvolatile memory device is performed for only one of the first and second mats, and

apply a second voltage to the third word-line for a second period of time longer than the first period of time when the first operation is performed for both of the first and second mats simultaneously.

2. The nonvolatile memory device of claim 1, wherein the third word-line is an unselected word-line and the first operation is a read operation.

3. The nonvolatile memory device of claim 2, wherein the row decoder is configured to:

apply a first read pass voltage to the third word-line during the first period of time when the read operation is performed on only one of the first mat and the second mat, and

apply a second read pass voltage to the third word-line during the second period of time when the read operation is performed on both of the first mat and the second mat simultaneously.

4. The nonvolatile memory device of claim 3, wherein a voltage level of the second read pass voltage is greater than a voltage level of the first read pass voltage.

5. The nonvolatile memory device of claim 2, wherein the row decoder is configured to:

apply a first pre-pulse to unselected at least one of the first and second string selection lines during a third period of time when the read operation is performed on only one of the first mat and the second mat, and

apply a second pre-pulse to the unselected at least one of the first and second string selection lines during a fourth period of time when the read operation is performed on both of the first mat and the second mat simultaneously.

6. The nonvolatile memory device of claim 5, wherein the fourth period of time is longer than the third period of time, and

wherein a voltage level of the second pre-pulse is greater than a voltage level of the first pre-pulse.

7. The nonvolatile memory device of claim 2, wherein the row decoder is configured to:

apply a first post-pulse to unselected at least one of the first and second string selection lines after the unselected at least one of the first and second string selection lines is discharged with a ground voltage during a third period of time when the read operation is performed on only one of the first mat and the second mat, and

apply a second post-pulse to the unselected at least one of the first and second string selection lines after the unselected at least one of the first and second string selection lines is discharged with the ground voltage during a fourth period of time when the read operation is performed on both of the first mat and the second mat simultaneously.

8. The nonvolatile memory device of claim 7, wherein the fourth period of time is longer than the third period of time, and

wherein a voltage level of the second post-pulse is greater than a voltage level of the first post-pulse.

9. The nonvolatile memory device of claim 1, wherein the third word-line is a selected word-line and the first operation is a program operation,

wherein the row decoder is configured to:

when only one of the first and second mats operates for programming data in the operating mat, apply a first program pass voltage to the third word-line, apply a first program voltage to the third word-line after the first program pass voltage is applied, and apply a first program verification voltage to the third word-line for a third period of time after the first program voltage is applied, and

when both of the first and second mats simultaneously operate for programming data in the operating mats, apply a second program pass voltage to the third word-line, apply a second program voltage to the third word-line after the second program pass voltage is applied, and apply a second program verification voltage to the third word-line for the second period of time after the second program voltage is applied, and

wherein a voltage level of the second program verification voltage is greater than a voltage level of the first program verification voltage.

10. The nonvolatile memory device of claim 1, wherein the third word-line is an unselected word-line and the first operation is a program operation,

wherein the row decoder is configured to:

when only one of the first and second mats operates for programming data in the operating mat, apply a first verification pass voltage to the third word-line for a third period of time, and

when both of the first and second mats simultaneously operate for programming data in the operating mats, apply a second verification pass voltage to the third word-line for a fourth period of time, and

wherein a voltage level of the second verification pass voltage is greater than a voltage level of the first verification pass voltage.

11. A nonvolatile memory device comprising:

a memory cell region including a first metal pad;

a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad;

a memory cell array in the memory cell region, the memory cell array including a plurality of mats, each of the plurality of mats including a plurality of cell strings, wherein;

a first cell string of a first mat of the plurality of mats is connected to a plurality of first word-lines, a first bit-line and a first string selection line,

a second cell string of a second mat of the plurality of mats is connected to a plurality of second word-lines, a second bit-line and a second string selection line,

the first and second cell strings are located perpendicular to a substrate respectively, and

each of the first and second cell strings includes at least one ground selection transistor, a plurality of memory cells, and at least one string selection transistor coupled in series with each other; and

a row decoder in the peripheral circuit region, connected to the plurality of first and second word-lines, the first and second string selection lines, and configured to apply corresponding word-line voltages to the plurality of first and second word-lines, wherein the row decoder is configured to;

apply a first voltage to a third word-line among the plurality of first and second word-lines through the first metal pad and the second metal pad for a first period of time when a first operation of the nonvolatile memory device is performed for only one of the first and second mats, and

apply a second voltage to the third word-line through the first metal pad and the second metal pad for a second period of time different from the first period of time when the first operation is performed for both of the first and second mats simultaneously.

12. The nonvolatile memory device of claim 11, wherein the memory cell region further includes:

a stair region; and

a plurality of vertical pass transistors in the stair region, and each of the vertical pass transistors including a vertical channel,

wherein the plurality of first and second word-lines are stacked in a vertical direction, and

wherein the row decoder is configured to apply the word-line voltages to the plurality of first and second word-lines through the plurality of vertical pass transistors.

13. The nonvolatile memory device of claim 12, wherein the memory cell region further includes:

a ground selection line in a layer on the plurality of first and second of word lines;

a common source line in a layer on the ground selection line;

a string selection line in a layer under the plurality of first and second of word lines; and

a plurality of driving signal lines are disposed at the same level as the common source line, and

wherein each of the plurality of first and second word-lines form a stair shape in the stair region.

14. The nonvolatile memory device of claim 13, wherein each of the plurality of vertical pass transistors is connected between a corresponding word line among each of the plurality of first and second word lines and a corresponding driving signal line among the plurality of driving signal lines.

15. The nonvolatile memory device of claim 13, wherein the peripheral circuit region further includes a normal pass transistor connected to the ground selection line, and

wherein the normal pass transistor includes a horizontal channel.

16. The nonvolatile memory device of claim 11, wherein the third word-line is an unselected word-line and the first operation is a read operation.

17. The nonvolatile memory device of claim 16, wherein the row decoder is configured to:

apply a first pre-pulse to unselected at least one of the first and second string selection lines during a third period of time when the read operation is performed on only one of the first mat and the second mat, and

apply a second pre-pulse to the unselected at least one of the first and second string selection lines during a fourth period of time when the read operation is performed on both of the first mat and the second mat simultaneously.

18. The nonvolatile memory device of claim 11, wherein the first operation is a program operation.

19. The nonvolatile memory device of claim 18, wherein the row decoder is configured to:

when only one of the first and second mats operates for programming data in the operating mat, apply a first program pass voltage to the third word-line, apply a first program voltage to the third word-line after the first program pass voltage is applied, and apply a first program verification voltage to the third word-line for a third period of time after the first program voltage is applied, and

when both of the first and second mats simultaneously operate for programming data in the operating mats, apply a second program pass voltage to the third word-line, apply a second program voltage to the third word-line after the second program pass voltage is applied, and apply a second program verification voltage to the third word-line for a fourth period of time longer than the first period of time after the second program voltage is applied.

20. The nonvolatile memory device of claim 19,

wherein the first program pass voltage, the first program voltage, the first program verification voltage are applied during a single operation, and

wherein the second program pass voltage, the second program voltage, the second program verification voltage are applied during another single operation.