Physical vapor deposition process for semiconductor interconnection structures

• US 11,018,055 B2
• Filed: 12/20/2019
• Issued: 05/25/2021
• Est. Priority Date: 11/28/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yang, Nai-Hao, Su, Hung-Wen, Chen, Kuan-Chia
• Primary Examiner(s): Kim, Tong-Ho
• Application Number:
  US16/722,433
• Publication Number:
  US 20200144112A1
• Time in Patent Office: 522 Days
• Field of Search: 257751
• CPC Class Codes: H01L 21/2855 by physical means, e.g. sputtering, evaporation H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/67103 mainly by conduction
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers

Abstract

The present disclosure provides methods for forming a conductive fill material (e.g., a conductive feature) by a physical vapor deposition (PVD) process. In one embodiment, a method of forming a conductive fill material on a substrate includes maintaining a first substrate temperature at a first range for a first period of time while forming a pre-layer of a conductive fill material on a substrate, providing a thermal energy to the substrate to maintain the substrate at a second substrate temperature at a second range for a second period of time, wherein the second substrate temperature is higher than the first substrate temperature, and continuously providing the thermal energy to the substrate to maintain the substrate a third substrate temperature at a third range for a third period of time to form a bulk layer of the conductive fill material on the substrate.

Claims

1. A method of forming a semiconductor device, the method comprising:

forming a first dielectric layer over a substrate;

forming a second dielectric layer over the first dielectric layer;

forming an opening in the second dielectric layer to expose an electrically conductive feature in the first dielectric layer;

lining sidewalls and a bottom of the opening with a barrier layer;

forming a pre-layer of an electrically conductive fill material over the barrier layer while the substrate is maintained at a first temperature;

after the pre-layer is formed, performing a thermal process to reflow the pre-layer, wherein during the thermal process, a temperature of the substrate is ramped up from the first temperature to a second temperature linearly or in discrete steps; and

after the thermal process, fill the opening with the electrically conductive fill material while the substrate is maintained at a third temperature.

2. The method of claim 1, wherein the third temperature higher than the first temperature.

3. The method of claim 2, wherein the third temperature is lower than the second temperature.

4. The method of claim 2, wherein the first temperature is a room temperature.

5. The method of claim 1, wherein forming the pre-layer comprises:

applying a first bias power to a substrate support pedestal on which the substrate is positioned; and

subsequently applying a second bias power to the substrate support pedestal, wherein the second bias power is greater than the first bias power.

6. The method of claim 5, wherein fill the opening comprises applying a third bias power to the substrate support pedestal, wherein the third bias power is greater than the first bias power but less than the second bias power.

7. The method of claim 1, wherein forming the pre-layer is performed in a first process chamber, and the thermal process is performed in a second process chamber different from the first process chamber.

8. The method of claim 7, wherein filling the opening is performed in the second process chamber.

9. A method of forming a semiconductor device, the method comprising:

forming a pre-layer of a conductive fill material along sidewalls and a bottom of an opening in a dielectric layer, wherein the dielectric layer is formed over a substrate, wherein forming the pre-layer comprises performing a first physical vapor deposition (PVD) process, wherein forming the pre-layer comprises;

applying a first bias power to a substrate support pedestal on which the substrate is positioned for a first period of time; and

after applying the first bias power for the first period of time, applying a second bias power to the substrate support pedestal for a second period of time, wherein the second bias power is greater than the first bias power;

performing a thermal process to change a profile of the pre-layer; and

after the thermal process, filling the opening with the conductive fill material.

10. The method of claim 9, wherein the thermal process reduces a thickness of a corner portion of the pre-layer and increases a thickness of a bottom portion of the pre-layer, wherein the corner portion is disposed at a corner of the dielectric layer at a top of the opening, and the bottom portion is disposed at the bottom of the opening.

11. The method of claim 9, wherein the pre-layer is formed at a first temperature, wherein the thermal process is performed by ramping up a temperature of the pre-layer from the first temperature to a second temperature higher than the first temperature linearly or in discrete steps.

12. The method of claim 11, wherein filling the opening is performed at a third temperature higher than the first temperature.

13. The method of claim 9, wherein filling the opening comprises performing a second PVD process, wherein filling the opening comprises:

applying a third bias power to the substrate support pedestal for a third period of time, wherein the third bias power is greater than the first bias power and smaller than the second bias power.

14. The method of claim 13, wherein no bias power is applied to the substrate support pedestal during the thermal process.

15. The method of claim 9, wherein forming the pre-layer is performed in a first process chamber, wherein the thermal process and filling the opening are performed in a second process chamber different from the first process chamber.

16. A method of forming a semiconductor device, the method comprising:

maintaining a substrate at a first temperature while forming a pre-layer of a conductive fill material along sidewalls and a bottom of an opening in a dielectric layer over the substrate;

reflowing the pre-layer by increasing a temperature of the substrate from the first temperature to a second temperature; and

maintaining the substrate at a third temperature while forming a bulk layer of the conductive fill material to fill the opening, wherein the pre-layered is formed in a first process chamber, wherein the reflowing the pre-layer and forming the bulk layer are performed in a second process chamber different from the first process chamber.

17. The method of claim 16, wherein reflowing the pre-layer comprises heating the substrate to a temperature between about 200 degrees and about 400 degrees Celsius.

18. The method of claim 16, wherein the third temperature is lower than the second temperature.

19. The method of claim 16, wherein reflowing the pre-layer comprises ramping up the temperature of the substrate from the first temperature to the second temperature linearly or in discrete steps.

20. The method of claim 16, wherein forming the pre-layer comprises performing a first physical vapor deposition (PVD) process, and forming the bulk layer comprises performing a second PVD process, wherein performing the first PVD process comprises:

applying a first bias power for a first period of time; and

subsequently applying a second bias power higher than the first bias power for a second period of time; and

wherein performing the second PVD process comprises applying a third bias power for a third period of time, the third bias power being greater than the first bias power and lower than the second bias power.