Fabrication of vertical fin transistor with multiple threshold voltages

• US 11,018,254 B2
• Filed: 03/31/2016
• Issued: 05/25/2021
• Est. Priority Date: 03/31/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Balakrishnan, Karthik, Cheng, Kangguo, Hashemi, Pouya, Reznicek, Alexander
• Primary Examiner(s): Wilczewski, Mary A
• Assistant Examiner(s): Chiu, Tsz K
• Application Number:
  US15/086,542
• Publication Number:
  US 20170288056A1
• Time in Patent Office: 1,881 Days
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/02252 formation by plasma treatment, e.g. plasma oxidation of the substrate after treatment of an insulating film by plasma H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/0825 Combination of vertical direct transistors of the same conductivity type having different characteristics,(e.g. Darlington transistors)
• CPC Class Codes: H01L 27/0828 Combination of direct and inverse vertical transistors
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10K 2101/80 Composition varying spatially, e.g. having a spatial gradient

Abstract

A vertical fin field effect transistor including a doped region in a substrate, wherein the doped region has the same crystal orientation as the substrate, a first portion of a vertical fin on the doped region, wherein the first portion of the vertical fin has the same crystal orientation as the substrate and a first portion width, a second portion of the vertical fin on the first portion of the vertical fin, wherein the second portion of the vertical fin has the same crystal orientation as the first portion of the vertical fin, and the second portion of the vertical fin has a second portion width less than the first portion width, a gate structure on the second portion of the vertical fin, and a source/drain region on the top of the second portion of the vertical fin.

Claims

1. A vertical fin field effect transistor, comprising:

a first doped region in a substrate, wherein the first doped region has the same crystal orientation as the substrate;

a first portion of a vertical fin on the first doped region, wherein the first portion of the vertical fin is silicon-germanium, has the same crystal orientation as the substrate, and a first portion width;

a second portion of the vertical fin on the first portion of the vertical fin, wherein the second portion of the vertical fin is silicon-germanium, has the same crystal orientation as the first portion of the vertical fin, and the second portion of the vertical fin has a second portion width less than the first portion width that exposes a top surface of the first portion of the vertical fin, wherein the second portion of the vertical fin has a higher germanium concentration than the first portion of a vertical fin;

a gate structure on the second portion of the vertical fin; and

a source/drain region on the top of the second portion of the vertical fin.

2. The vertical fin field effect transistor of claim 1, wherein the source/drain region has the same crystal orientation as the vertical fin.

3. The vertical fin field effect transistor of claim 2, which further comprises a bottom spacer between at least the drain region and the gate structure, and a top spacer between the gate structure and the source/drain region on the second portion of the vertical fin.

4. The vertical fin field effect transistor of claim 1, wherein the second portion of the vertical fin has a germanium concentration in the range of about 20 at. % Ge to about 50 at. % Ge.

5. The vertical fin field effect transistor of claim 1, wherein the second portion of the vertical fin has a vertically graded germanium concentration.

6. A vertical fin field effect transistor, comprising:

a first doped region in a substrate, wherein the first doped region has the same crystal orientation as the substrate;

a bottom spacer on the first doped region, wherein the bottom spacer has a top surface;

a first portion of a vertical fin on the first doped region, wherein the first portion of the vertical fin has the same crystal orientation as the substrate, wherein the first portion of the vertical fin has a top surface that is at or below the top surface of the bottom spacer;

a second portion of the vertical fin on the first portion of the vertical fin, wherein the second portion of the vertical fin has the same crystal orientation as the first portion of the vertical fin, and the second portion of the vertical fin extends above the top surface of the bottom spacer, wherein the width of the second portion of the vertical fin is less than the width of the first portion of the vertical fin, wherein the first portion of the vertical fin and the second portion of the vertical fin are silicon germanium, and the second portion of the vertical fin has a greater percentage of germanium than the first portion of the vertical fin;

a gate structure on the second portion of the vertical fin;

a top spacer on the gate structure; and

a source/drain region on the top of the second portion of the vertical fin.

7. The vertical fin field effect transistor of claim 6, wherein the second portion of the vertical fin has a width in a range of about range of about 7 nm to about 18 nm, and the first portion of the vertical fin has a width in a range of about 10 nm to about 20 nm.

8. The vertical fin field effect transistor of claim 7, wherein the second portion of the vertical fin has a germanium concentration in the range of about 20 at. % Ge to about 50 at. % Ge.

9. The vertical fin field effect transistor of claim 8, wherein the second portion of the vertical fin has a vertically graded germanium concentration.