Semiconductor package and methods of forming the same

• US 11,031,289 B2
• Filed: 04/30/2019
• Issued: 06/08/2021
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tu, Meng-Che, Chen, Wei-Chih, Liao, Sih-Hao, Hu, Yu-Hsiang, Kuo, Hung-Jui, Yu, Chen-Hua
• Primary Examiner(s): Page, Dale E
• Assistant Examiner(s): Baptiste, Wilner Jean
• Application Number:
  US16/399,710
• Publication Number:
  US 20200135567A1
• Time in Patent Office: 770 Days
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/82 to produce devices, e.g. integrated circuits, each consisting of a plurality of components
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/214 Connecting portions
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 24/08 of an individual bonding area
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms

Abstract

A method of forming a semiconductor device includes forming a first dielectric layer over a front side of a wafer, the wafer having a plurality of dies at the front side of the wafer, the first dielectric layer having a first shrinkage ratio smaller than a first pre-determined threshold; curing the first dielectric layer at a first temperature, where after curing the first dielectric layer, a first distance between a highest point of an upper surface of the first dielectric layer and a lowest point of the upper surface of the first dielectric layer is smaller than a second pre-determined threshold; thinning the wafer from a backside of the wafer; and performing a dicing process to separate the plurality of dies into individual dies.

Claims

1. A method of forming a semiconductor device, the method comprising:

forming a first dielectric layer over a passivation layer of a die and over a die connector of the die, the die connector extending through the passivation layer;

curing the first dielectric layer, wherein after curing the first dielectric layer, the first dielectric layer has a curved upper surface distal to the passivation layer, wherein the curved upper surface comprises;

a first region over and contacting the die connector; and

a second region laterally adjacent to the die connector, wherein the first region extends further from the passivation layer than the second region, wherein a first distance between the first region and the second region is larger than a first pre-determined threshold of distance;

forming a second dielectric layer over the cured first dielectric layer; and

curing the second dielectric layer, wherein after curing the second dielectric layer, the first dielectric layer extends along and contacts an upper surface of the die connector and sidewalls of the die connector, and an upper surface of the second dielectric layer distal to the passivation layer comprises;

a third region over and contacting the first region; and

a fourth region over the second region, wherein a second distance between the third region and the fourth region is smaller than the first pre-determined threshold of distance.

2. The method of claim 1, wherein before curing the second dielectric layer, the die is in a substrate, wherein the method further comprises performing a dicing process after curing the second dielectric layer, wherein the dicing process separates the die from other dies in the substrate.

3. The method of claim 1, further comprising:

performing a thinning process to reduce a thickness of the die after curing the second dielectric layer;

attaching the die with reduced thickness to a carrier;

forming a molding material over the carrier and over the die; and

forming a redistribution structure over the molding material, the redistribution structure being electrically coupled to the die.

4. The method of claim 3, further comprising:

performing a planarization process after forming the molding material, wherein the planarization process removes at least portions of the molding material and exposes the die connector, wherein after the planarization process, the die connector, the first dielectric layer, and the second dielectric layer have a same level upper surface.

5. The method of claim 4, wherein the planarization process removes portions of the first dielectric layer and portions of the second dielectric layer, wherein after the planarization process, remaining portions of the first dielectric layer physically contact the die connector, and remaining portions of the second dielectric layer are separated from the die connector by the remaining portions of the first dielectric layer.

6. The method of claim 3, further comprising:

performing a planarization process after forming the molding material, wherein the planarization process removes the second dielectric layer and portions of the first dielectric layer, wherein after the planarization process, the die connector and the first dielectric layer have a same level upper surface.

7. The method of claim 6, wherein the planarization process further removes upper portions of the die connector.

8. The method of claim 1, wherein the first pre-determined threshold of distance is 4 μ

m.

9. The method of claim 1, wherein the first dielectric layer is formed of a material comprising PI, PBO, or polyacrylate, and the second dielectric layer is formed of a material comprising epoxy or phenolic epoxy.

10. The method of claim 1, wherein the first dielectric layer has a first shrinkage ratio between about 50% and about 80%, and the second dielectric layer has a second shrinkage ratio less than about 5%.

11. The method of claim 1, wherein the first dielectric layer is cured at a first temperature, and the second dielectric layer is cured at a second temperature lower than the first temperature.

12. The method of claim 1, wherein the first dielectric layer and the second dielectric layer are cured at a same temperature.

13. A method of forming a semiconductor device, the method comprising:

forming a first dielectric layer over a front side of a wafer, the wafer having a plurality of dies at the front side of the wafer, the first dielectric layer having a first shrinkage ratio smaller than a first pre-determined threshold of shrinkage ratio;

curing the first dielectric layer at a first temperature, wherein after curing the first dielectric layer, a first distance between a highest point of an upper surface of the first dielectric layer and a lowest point of the upper surface of the first dielectric layer is smaller than a second pre-determined threshold of distance;

thinning the wafer from a backside of the wafer; and

performing a dicing process to separate the plurality of dies into individual dies.

14. The method of claim 13, wherein the first pre-determined threshold of shrinkage ratio is 1%, and the second pre-determined threshold of distance is 4 μ

m.

15. The method of claim 13, further comprising:

forming a second dielectric layer over the front side of the wafer before forming the first dielectric layer, the second dielectric layer having a second shrinkage ratio larger than the first pre-determined threshold of shrinkage ratio; and

curing the second dielectric layer after forming the second dielectric layer and before forming the first dielectric layer, wherein after curing the second dielectric layer, a second distance between a highest point of an upper surface of the second dielectric layer and a lowest point of the upper surface of the second dielectric layer is larger than the second pre-determined threshold of distance.

16. The method of claim 15, wherein curing the first dielectric layer is performed at first temperature, and wherein curing the second dielectric layer is performed at a second temperature higher than the first temperature.

17. A method of forming a semiconductor device, the method comprising:

forming a first dielectric layer over a passivation layer of a die, the die having a die connector extending through the passivation layer, the first dielectric layer having a first portion in physical contact with the die connector and having a second portion spaced apart from the die connector, an upper surface of the first portion of the first dielectric layer extending further from the passivation layer than an upper surface of the second portion of the first dielectric layer; and

forming a second dielectric layer over the upper surface of the second portion of the first dielectric layer, wherein the die connector, the second dielectric layer, and the first portion of the first dielectric layer have a coplanar upper surface.

18. The method of claim 17, wherein the first dielectric layer has a first shrinkage ratio that is larger than a second shrinkage ratio of the second dielectric layer.

19. The method of claim 18, wherein the first shrinkage ratio is between about 50% and about 80%, and the second shrinkage ratio is less than about 1%.

20. The method of claim 17, further comprising:

forming a molding material around the die, around the first dielectric layer and around the second dielectric layer, an upper surface of the molding material being level with the upper surface of the second dielectric layer; and

forming a redistribution structure over the molding material and electrically coupled to the die.