Array substrate, display panel having the same, and method of fabricating array substrate

• US 11,063,095 B2
• Filed: 06/01/2017
• Issued: 07/13/2021
• Est. Priority Date: 06/01/2017
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Hu, Chunjing
• Primary Examiner(s): Choi, Calvin Y
• Application Number:
  US15/780,767
• Publication Number:
  US 20200251540A1
• Time in Patent Office: 1,503 Days
• Field of Search: 257 40
• CPC Class Codes: H10K 59/1201 Manufacture or treatment
• CPC Class Codes: H10K 59/121 characterised by the geometry or disposition of pixel elements
• CPC Class Codes: H10K 59/122 Pixel-defining structures or layers, e.g. banks
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 59/35 comprising red-green-blue [RGB] subpixels
• CPC Class Codes: H10K 71/00 Manufacture or treatment specially adapted for the organic devices covered by this subclass

Abstract

The present application discloses an array substrate having a subpixel region and an inter-subpixel region. The array substrate includes a base substrate; a thin film transistor on the base substrate and including a drain electrode; a passivation layer on a side of the thin film transistor distal to the base substrate; a pixel electrode layer on a side of the passivation layer distal to the base substrate; a pixel definition layer in the inter-subpixel region; and an organic light emitting layer in the subpixel region on a side of the pixel electrode layer distal to the passivation layer. The array substrate includes a via extending through the passivation layer. The pixel electrode layer is electrically connected to the drain electrode of the thin film transistor through the via. The via is in the subpixel region.

Claims

1. An array substrate having a subpixel region and an inter-subpixel region, comprising:

a base substrate;

a thin film transistor on the base substrate and comprising a drain electrode;

a passivation layer on a side of the thin film transistor distal to the base substrate;

a pixel electrode layer on a side of the passivation layer distal to the base substrate;

a pixel definition layer in the inter-subpixel region on a side of the pixel electrode layer distal to the passivation layer and defining the subpixel region; and

an organic layer comprising an organic light emitting layer in the subpixel region on a side of the pixel electrode layer distal to the passivation layer;

wherein the array substrate comprises a via extending through the passivation layer;

the pixel electrode layer is electrically connected to the drain electrode of the thin film transistor through the via;

the organic layer has a non-uniform thickness, with a thickness in a peripheral part of the organic layer greater than a thickness in a central part of the organic layer;

a projection of the peripheral part on the base substrate completely covers a projection of the via on the base substrate; and

the projection of the via on the base substrate is completely non-overlapping with a projection of the pixel definition layer in the array substrate on the base substrate.

2. The array substrate of claim 1, wherein a projection of the drain electrode on the base substrate is completely non-overlapping with that of the pixel definition layer in the array substrate.

3. The array substrate of claim 1, wherein a projection of a light emitting region of the organic light emitting layer on the base substrate completely covers that of the thin film transistor.

4. The array substrate of claim 1, wherein a projection of a light emitting region of the organic light emitting layer on the base substrate substantially covers that of the via.

5. The array substrate of claim 1, wherein the drain electrode of the thin film transistor is in the subpixel region.

6. The array substrate of claim 5, wherein a projection of the drain electrode on the base substrate is substantially non-overlapping with that of any pixel definition layer in the array substrate.

7. The array substrate of claim 5, wherein a projection of the organic light emitting layer on the base substrate substantially covers that of the drain electrode.

8. The array substrate of claim 5, wherein a projection of a light emitting region of the organic light emitting layer on the base substrate substantially covers that of the drain electrode.

9. The array substrate of claim 5, wherein a projection of a light emitting region of the organic light emitting layer on the base substrate substantially covers that of the thin film transistor.

10. The array substrate of claim 1, comprising a plurality of subpixel areas each of which having a shape elongated along a first direction;

wherein a width of the subpixel region in each of the plurality of subpixel areas along the first direction is greater than a pitch of the plurality of subpixel areas along the first direction minus 30 μ

m.

11. The array substrate of claim 10, wherein the width of the subpixel region in each of the plurality of subpixel areas along the first direction is approximately the pitch minus 17 μ

m.

12. The array substrate of claim 1, comprising a plurality of subpixel areas each of which having a shape elongated along a first direction;

wherein a width of the pixel definition layer between adjacent two subpixel regions respectively in adjacent two subpixel areas along the first direction is smaller than 30 μ

m.

13. The array substrate of claim 12, wherein the width of the pixel definition layer between adjacent two subpixel regions respectively in adjacent two subpixel areas along the first direction is approximately 17 μ

m.

14. The array substrate of claim 1, comprising a plurality of subpixel areas each of which having a shape elongated along a first direction;

wherein the plurality of subpixel areas have a pitch along the first direction; and

a width of the organic light emitting layer in each of the plurality of subpixel areas along the first direction is greater than the pitch minus 30 μ

m.

15. The array substrate of claim 14, wherein the width of the organic light emitting layer in each of the plurality of subpixel areas along the first direction is approximately the pitch minus 17 μ

m.

16. The array substrate of claim 1, wherein a first portion of the pixel electrode layer corresponding to the via has a first surface distal to the base substrate;

and

the first surface is substantially level with a surface of other portions of the pixel electrode layer distal to the base substrate.

17. The array substrate of claim 16, comprising a solidified silver paste in the via.

18. The array substrate of claim 1, wherein the pixel electrode layer comprises a concaved portion and a convex portion

a maximum width of the convex portion in a cross-section along a cross-section plane intersecting the organic layer, the pixel electrode layer, the passivation layer, and the base substrate is greater than or equal to a maximum width of the concave portion in the cross-section plane;

the convex portion extends through the via to connect to the drain electrode; and

the peripheral part fills in the concave portion.

19. A display panel, comprising the array substrate of claim 1.

20. A method of fabricating an array substrate, comprising:

forming a thin film transistor on a base substrate, the thin film transistor being formed to comprises a drain electrode;

forming a passivation layer on a side of the thin film transistor distal to the base substrate;

forming a pixel electrode layer on a side of the passivation layer distal to the base substrate;

forming a pixel definition layer on a side of the pixel electrode layer distal to the passivation layer and defining a subpixel region;

forming an organic light emitting layer on a side of the pixel electrode layer distal to the passivation layer; and

forming a via extending through the passivation layer, the pixel electrode layer being formed to be electrically connected to the drain electrode of the thin film transistor through the via;

wherein the pixel definition layer defines a subpixel region of the array substrate;

the organic light emitting layer is formed in the subpixel region;

the organic light emitting layer is formed to have a non-uniform thickness, with a thickness in a peripheral part of the organic light emitting layer greater than a thickness in a central part of the organic light emitting layer;

a projection of the peripheral part on the base substrate completely covers a projection of the via on the base substrate; and

the projection of the via on the base substrate is completely non-overlapping with a projection of the pixel definition layer in the array substrate on the base substrate.