Array substrate and method of manufacturing the same, display device

• US 11,069,719 B2
• Filed: 07/03/2019
• Issued: 07/20/2021
• Est. Priority Date: 07/06/2018
• Status: Active Grant

• Current Assignee: Beijing BOE Display Technology Co Ltd (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Display Technology Co Ltd (BOE Technology Group Co., Ltd.)
• Inventors: Xu, Wenqing, Li, Xiaolong, Zhang, Xiaoxiang, Liu, Mingxuan, Wu, Zumou, Guo, Huibin, Song, Yongzhi
• Primary Examiner(s): Nguyen, Cuong B
• Application Number:
  US16/503,053
• Publication Number:
  US 20200013804A1
• Time in Patent Office: 748 Days
• CPC Class Codes: G02F 1/13606 having means for reducing parasitic capacitance
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136277 formed on a semiconductor substrate, e.g. of silicon
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1262 with a particular formation, treatment or coating of the substrate
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H10K 59/122 Pixel-defining structures or layers, e.g. banks
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/124 Insulating layers formed between TFT elements and OLED elements
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals

Abstract

An array substrate includes a base substrate, a plurality of signal lines disposed at a side of the base substrate, and an organic layer disposed at a side of the plurality of signal lines facing away from the base substrate. The organic layer includes at least one auxiliary portion and a reference portion surrounding the at least one auxiliary portion, and a thickness of each auxiliary portion is less than a thickness of the reference portion.

Claims

1. An array substrate, comprising:

a base substrate;

a plurality of signal lines disposed at a side of the base substrate; and

an organic layer disposed at a side of the plurality of signal lines facing away from the base substrate, wherein

the organic layer includes at least one auxiliary portion and a reference portion surrounding the at least one auxiliary portion, and a thickness of each auxiliary portion is less than a thickness of the reference portion;

the thickness of each auxiliary portion is less than or equal to one third of the thickness of the reference portion, and the thickness of each auxiliary portion is less than or equal to a value in a range of 0.8 μ

m to 1.2 μ

m; and

the at least one auxiliary portion includes a plurality of auxiliary portions, and thicknesses of the plurality of auxiliary portions are the same.

2. The array substrate according to claim 1, wherein an orthographic projection of each auxiliary portion on the base substrate is located outside a range of an orthographic projection of the plurality of signal lines on the base substrate.

3. The array substrate according to claim 2, further comprising at least one electrode disposed at a side of the organic layer facing away from the base substrate.

4. The array substrate according to claim 3, wherein the reference portion is coupled to the at least one auxiliary portion.

5. The array substrate according to claim 3, wherein the plurality of signal lines are selected from a group consisting of:

a plurality of gate lines, a plurality of data lines, a plurality of common electrode lines, and a combination thereof.

6. The array substrate according to claim 3, wherein

the at least one electrode includes at least one pixel electrode;

or the at least one electrode includes at least one common electrode;

or

the at least one electrode includes at least one pixel electrode and at least one common electrode.

7. The array substrate according to claim 3, further comprising a plurality of thin film transistors disposed between the base substrate and the reference portion of the organic layer.

8. The array substrate according to claim 7, wherein an orthographic projection of each auxiliary portion on the base substrate is further located outside a range of an orthographic projection of the plurality of thin film transistors on the base substrate.

9. A display device, comprising the array substrate according to claim 1.

10. A method of manufacturing an array substrate, comprising:

providing a base substrate;

forming a plurality of signal lines at the base substrate; and

forming an organic layer at a side of the plurality of signal lines facing away from the base substrate, wherein

the organic layer includes at least one auxiliary portion and a reference portion surrounding the at least one auxiliary portion, and a thickness of each auxiliary portion is less than a thickness of the reference portion;

the thickness of each auxiliary portion is less than or equal to one third of the thickness of the reference portion, and the thickness of each auxiliary portion is less than or equal to a value in a range of 0.8 μ

m to 1.2 μ

m; and

the at least one auxiliary portion includes a plurality of auxiliary portions, and thicknesses of the plurality of auxiliary portions are the same.

11. The method of manufacturing the array substrate according to claim 10, wherein an orthographic projection of each auxiliary portion on the base substrate is located outside a range of an orthographic projection of the plurality of signal lines on the base substrate.

12. The method of manufacturing the array substrate according to claim 11, further comprising forming at least one electrode at a side of the organic layer facing away from the base substrate.

13. The method of manufacturing the array substrate according to claim 12, wherein the step of forming the organic layer at the side of the plurality of signal lines facing away from the base substrate, includes:

forming an organic material film at the side of the plurality of signal lines facing away from the base substrate;

forming a photoresist layer on the surface of the organic material film facing away from the base substrate;

exposing the photoresist layer through a half-tone mask and developing the exposed photoresist layer, so as to form a patterned photoresist layer; and

etching the organic material film by using the patterned photoresist layer as a mask, so that the etched organic material film is the organic layer including a reference portion and at least one auxiliary portion.

14. The method of manufacturing the array substrate according to claim 13, wherein after the step of forming the organic layer at the side of the plurality of signal lines facing away from the base substrate, the manufacturing method further comprising:

drying the organic layer.

15. The method of manufacturing the array substrate according to claim 12, wherein the step of forming the plurality of signal lines at a side of the base substrate, includes:

forming a plurality lines selected from a group consisting of a plurality of gate lines, a plurality of data lines, a plurality of common electrode lines, and a combination thereof.

16. The method of manufacturing the array substrate according to claim 12, wherein the step of forming the at least one electrode at the side of the organic layer facing away from the base substrate, includes:

forming at least one pixel electrode at the side of the organic layer facing away from the base substrate;

or forming at least one common electrode at the side of the organic layer facing away from the base substrate;

or

forming at least one pixel electrode and at least one common electrode at the side of the organic layer facing away from the base substrate.