Method of forming a semiconductor structure

• US 11,088,023 B2
• Filed: 03/21/2018
• Issued: 08/10/2021
• Est. Priority Date: 05/31/2017
• Status: Active Grant

• Current Assignee: Fujian Jinhua Integrated Circuit Co., Ltd., United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chen, Pin-Hong, Tsai, Chih-Chieh, Chen, Tzu-Chieh, Chang, Kai-Jiun, Wu, Chia-Chen, Huang, Yi-An, Cheng, Tsun-Min, Chen, Yi-Wei, Liu, Wei-Hsin
• Primary Examiner(s): Lee, Kyoung
• Assistant Examiner(s): Sylvia, Christina A
• Application Number:
  US15/927,106
• Publication Number:
  US 20180350673A1
• Time in Patent Office: 1,238 Days
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/76847 the layer being positioned within the main fill metal
• CPC Class Codes: H01L 21/76876 for deposition from the gas phase, e.g. CVD
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug

Abstract

A method of forming a semiconductor structure includes providing a material layer having a recess formed therein. A first tungsten metal layer is formed at a first temperature and fills the recess. An anneal process at a second temperature is then performed, wherein the second temperature is higher than the first temperature.

Claims

1. A method of forming a semiconductor structure, comprising:

providing a material layer;

forming a recess in the material layer, wherein the material layer comprises a plurality of electrical connecting structures, each of the plurality of electrical connecting structures is formed by a second tungsten metal layer, and the recess is between two of the plurality of electrical connecting structures;

forming a first tungsten metal layer filling the recess at a first temperature; and

performing an anneal process in an inert ambient at a second temperature, wherein the second temperature is higher than the first temperature, the first temperature is between 250°

C. and 350°

C., and the second temperature is between 400°

C. and 500°

C.

2. The method of forming a semiconductor structure of claim 1, wherein the anneal process comprises a rapid thermal anneal process.

3. The method of forming a semiconductor structure of claim 1, wherein an operating time of the anneal process is not greater than one minute.

4. The method of forming a semiconductor structure of claim 3, wherein the anneal process comprises introducing nitrogen gas.

5. The method of forming a semiconductor structure of claim 1, wherein an average grain size of the first tungsten metal layer before performing the anneal process is smaller than 70 nanometers, and the average grain size of the first tungsten metal layer after performing the anneal process is between 70 nanometers and 100 nanometers.

6. The method of forming a semiconductor structure of claim 1, wherein an average grain size of the first tungsten metal layer after the anneal process increases by 40% to 50% with respect to the average grain size of the first tungsten metal layer before the anneal process.

7. The method of forming a semiconductor structure of claim 1, further comprising:

before forming the first tungsten metal layer, forming a tungsten nucleation layer at the first temperature to cover a sidewall of the recess and a bottom of the recess.

8. The method of forming a semiconductor structure of claim 7, wherein before the anneal process, an average grain size of the tungsten nucleation layer is not greater than 30 nanometers.

9. The method of forming a semiconductor structure of claim 7, further comprising forming a barrier between the tungsten nucleation layer and the material layer.

10. The method of forming a semiconductor structure of claim 1, wherein the second tungsten metal layer is formed at a third temperature.

11. The method of forming a semiconductor structure of claim 10, wherein the third temperature is between the first temperature and the second temperature.

12. The method of forming a semiconductor structure of claim 1, wherein before the anneal process, an average grain size of the second tungsten metal layer is greater than an average grain size of the first tungsten metal layer.

13. The method of forming a semiconductor structure of claim 12, wherein after the anneal process, the average grain size of the second tungsten metal layer is substantially equal to the average grain size of the first tungsten metal layer.

14. The method of forming a semiconductor structure of claim 1, wherein before the anneal process, an average grain size of the second tungsten metal layer is between 70 nanometers and 100 nanometers.