System and method to enhance solder joint reliability

• US 11,094,604 B2
• Filed: 06/27/2019
• Issued: 08/17/2021
• Est. Priority Date: 09/26/2017
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Yu, Lee Kong, Im, Sungjun, Lau, Chun Sean, Chin, Yoong Tatt, Gill, Paramjeet Singh, Teh, Weng-Hong
• Primary Examiner(s): Pham, Long
• Application Number:
  US16/455,660
• Publication Number:
  US 20190326194A1
• Time in Patent Office: 782 Days
• Field of Search: None
• CPC Class Codes: H01L 21/4871 Bases, plates or heatsinks
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2224/05 of an individual bonding area
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/13101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/81385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/81395 having an external coating, e.g. protective bond-through coating
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 2224/81908 involving monitoring, e.g. feedback loop
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/3185 the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 23/3675 characterised by the shape of the housing
• CPC Class Codes: H01L 23/3736 Metallic materials H01L23/3732, H01L23/3733, H01L23/3735, H01L23/3737, H01L23/3738 take precedence
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/16151 : Cap comprising an aperture, e.g. for pressure control, encapsulation
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/16235 : Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.

Claims

1. A method comprising:

identifying a failure profile of solder joints formed between a first component and a level of interconnects and between the level of interconnects and a second component; and

disposing a reliability cover over one or more surfaces of at least one of the first component and the second component based upon the failure profile,

wherein the reliability cover comprises a package level reliability cover that is disposed on at least a portion of an integrated circuit package, and wherein a second reliability cover comprises a die level reliability cover that is disposed on at least a portion of a die.

2. The method of claim 1, wherein the first component is the integrated circuit package.

3. The method of claim 2, wherein the second component is a printed circuit board.

4. The method of claim 3, wherein identifying the failure profile comprises identifying a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board.

5. The method of claim 3, wherein the reliability cover is disposed on the one or more surfaces of the integrated circuit package whose difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board is greater than a threshold value.

6. The method of claim 1, wherein the first component is a Si die, and the second component is a substrate of the integrated circuit package.

7. The method of claim 6, wherein identifying the failure profile comprises identifying a difference in a coefficient of thermal expansion between the substrate of the integrated circuit package and the Si die.

8. The method of claim 6, wherein the reliability cover is disposed over the one or more surfaces of the Si die whose difference in a coefficient of thermal expansion between the substrate of the integrated circuit package and the Si die is greater than a threshold value.

9. The method of claim 2, wherein the reliability cover is disposed over the integrated circuit package and covers a total area that is less than an entire top surface area of the integrated circuit package.

10. The method of claim 1, wherein the reliability cover is deposited as a film.

11. The method of claim 1, wherein the reliability cover is configured as a mechanical lid.

12. The method of claim 2, wherein an air release hole on a surface of the reliability cover vents air pressure from between the reliability cover and the integrated circuit package.

13. The method of claim 2, wherein a thickness of the reliability cover is scaled based on a height of the integrated circuit package, a coefficient of thermal expansion of the integrated circuit package, and a coefficient of thermal expansion of the reliability cover.

14. The method of claim 6, wherein the reliability cover comprises a die level reliability cover that is disposed on an interposer layer formed between the substrate of the integrated circuit package and the Si die.

15. The method of claim 3, wherein the reliability cover comprises one or more reliability cover portions, and each of the one or more reliability cover portions is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board by varying threshold values.

16. The method of claim 9, wherein the second component is a printed circuit board, and wherein the integrated circuit package is mounted to the printed circuit board via a plurality of solder balls.

17. The method of claim 16, wherein the total area corresponds to a failure profile of solder joints formed between the plurality of solder balls and the integrated circuit package and between the plurality of solder balls and the printed circuit board.

18. The method of claim 1, wherein the reliability cover is disposed along at least a portion of a perimeter of a top surface of the integrated circuit package.

19. The method of claim 1, wherein the reliability cover is disposed at one or more corners of a top surface of the integrated circuit package.

20. The method of claim 1, wherein the die is a Si die.