Semiconductor device and manufacturing method thereof

• US 11,133,328 B2
• Filed: 06/26/2019
• Issued: 09/28/2021
• Est. Priority Date: 07/17/2017
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Choi, Kang Sik
• Primary Examiner(s): Smith, Zandra V
• Assistant Examiner(s): Stevenson, Andre C
• Application Number:
  US16/453,448
• Publication Number:
  US 20190326320A1
• Time in Patent Office: 825 Days
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A semiconductor device includes: a stack structure including horizontal conductive patterns and interlayer insulating layers, which are alternately stacked; gate patterns overlapping with both ends of the stack structure under the stack structure, the gate patterns being spaced apart from each other; and a channel pattern including vertical parts penetrating the stack structure, and a connection part disposed under the stack structure, the connection part connecting the vertical parts.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

forming a sacrificial group having a buried pattern embedded therein;

forming a stack structure over the sacrificial group, wherein the stack structure includes first material layers and second material layers, which are alternately stacked, wherein the stack structure is divided into a first region overlapping with the buried pattern and a second region extending from the first region, and wherein the second region of the stack structure does not overlap with the buried pattern;

forming a hole penetrating the second region of the stack structure to expose the sacrificial group;

removing the sacrificial group;

forming a multi-layered memory layer and a channel layer within the hole, wherein the multi-layered memory layer and the channel layer extend along a sidewall of the buried pattern and a bottom surface of the buried pattern;

forming a slit exposing a sidewall of the stack structure therethrough by etching the first region of the stack structure through an etching process that is stopped when the buried pattern is exposed; and

separating the buried pattern into gate patterns by etching a portion of the buried pattern exposed through the slit.

2. The method of claim 1, wherein a width of the slit is narrower than that of the buried pattern.

3. The method of claim 1, wherein the buried pattern is formed of a material different from that of the first material layers and the second material layers.

4. The method of claim 1, wherein the separating of the buried pattern into the gate patterns includes forming a first through part that completely penetrates the buried pattern exposed through the slit.

5. The method of claim 4, comprising:

forming a protective layer by oxidizing a surface of the buried pattern exposed through the slit;

replacing the first material layers with third material layers through the slit; and

forming a spacer insulating layer extending along a sidewall of the first through part from a sidewall of the slit.

6. A method of manufacturing a semiconductor device, the method comprising:

forming a sacrificial group having a buried pattern embedded therein;

forming a stack structure over the sacrificial group, wherein the stack structure includes first material layers and second material layers, which are alternately stacked, wherein the stack structure is divided into a first region overlapping with the buried pattern and a second region extending from the first region, and wherein the second region of the stack structure does not overlap with the buried pattern;

forming a slit exposing a sidewall of the stack structure therethrough by etching the first region of the stack structure through an etching process that is stopped when the buried pattern is exposed; and

separating the buried pattern into gate patterns by etching a portion of the buried pattern exposed through the slit,

wherein the forming of the sacrificial group having the buried pattern embedded therein includes;

forming a first protective layer on a well structure;

forming a first sacrificial layer on the first protective layer;

forming a second protective layer on the first sacrificial layer;

forming a conductive layer on the second protective layer;

forming supporting poles penetrating the well structure from the conductive layer;

forming a first opening and the buried pattern by etching the conductive layer, the first opening exposing the supporting poles;

forming a third protective layer by oxidizing a surface of the buried pattern;

etching the third protective layer and the second protective layer through an etch-back process such that the third protective layer remains on a sidewall of the buried pattern, the second protective layer remains under the buried pattern, and the first sacrificial layer is exposed; and

filling a second sacrificial layer in the first opening.

7. The method of claim 6, comprising:

forming holes that expose the second sacrificial layer therethrough by penetrating the second region of the stack structure;

forming a second opening that exposes the first sacrificial layer and the third protective layer therethrough and is connected to the holes by removing the second sacrificial layer through the holes;

forming a third opening that opens a space between the buried pattern and the well structure by removing the first sacrificial layer;

forming a multi-layered memory layer that extends to the inside of the holes from the inside of a horizontal space including the second and third openings along a surface of the horizontal space and surfaces of the holes;

forming a channel layer on a surface of the multi-layered memory layer; and

forming a gap-fill insulating layer filled in the horizontal space and the holes on the channel layer.

8. The method of claim 7, further comprising forming a trench that penetrates the multi-layered memory layer, the channel layer, and the gap-fill insulating layer, which are exposed between the gate patterns,

wherein the multi-layered memory layer is separated into multi-layered memory patterns by the trench, the channel layer is separated into channel patterns by the trench, and the gap-fill insulating layer is separated into gap-fill insulating patterns by the trench.

9. The method of claim 8, wherein the forming of the trench includes:

forming an upper through part that extends to the inside of the gap-fill insulating layer by penetrating the multi-layered memory layer and the channel layer, which are exposed between the gate patterns, and defines a first end part of the channel pattern; and

forming a lower through part that exposes the well structure therethrough and defines a second end part of the channel pattern by removing portions of the gap-fill insulating layer and the channel layer under the gap-fill insulating layer through the upper though part.

10. The method of claim 9, further comprising:

forming a well contact line inside the lower through part to be in contact with the second end part of the channel pattern and the well structure;

forming an inter-well-source insulating layer on the well contact line; and

forming a source contact line in contact with the first end part of the channel pattern on the inter-well-source insulating layer.

11. The method of claim 10, further comprising:

before the forming of the lower through part, forming a channel protective layer protecting the first end part of the channel pattern on a sidewall of the upper through part; and

after the forming of the inter-well-source insulating layer, removing the channel protective layer.

12. The method of claim 10, wherein the well structure includes a first conductivity type dopant, and

the source contact line includes a second conductivity type dopant different from the first conductivity type dopant.

13. The method of claim 12, further comprising forming a source junction inside the channel pattern by diffusing the second conductivity type dopant in the source contact line into the channel pattern adjacent to the source contact line.

14. A method of manufacturing a semiconductor device, the method comprising:

forming a well structure including a first conductivity type dopant;

forming a sacrificial group over the well structure, wherein the sacrificial group has a conductive pattern embedded therein;

forming a stack structure over the sacrificial group, wherein the stack structure includes a first region overlapping with the conductive pattern and a second region extending from the first region;

forming holes that penetrate the second region of the stack structure;

opening a horizontal space by removing the sacrificial group through the holes;

forming a multi-layered memory layer extending to the inside of the holes from the inside of the horizontal space along a surface of the horizontal space and surfaces of the holes;

forming a channel layer on a surface of the multi-layered memory layer;

forming a gap-fill insulating layer that is filled in the horizontal space and the holes on the channel layer;

exposing the well structure by etching the first region of the stack structure, the conductive pattern, the multi-layered memory layer, the gap-fill insulating layer, and the channel layer;

forming a well contact line that connects the well structure and the channel layer; and

forming a source contact line that is connected to the channel layer on the top of the well contact line and includes a second conductivity type dopant.

15. The method of claim 14, wherein the exposing of the well structure includes:

forming a slit that exposes a side wall of the stack structure and the conductive pattern therethrough by etching the first region of the stack structure;

forming a first through part that separates the conductive pattern into gate patterns by etching the conductive pattern exposed through the slit;

forming a second through part that exposes the channel layer therethrough by etching the multi-layered memory layer exposed through the first through part;

forming a third through part that exposes the gap-fill insulating layer therethrough by etching the channel layer exposed through the second through part; and

forming a fourth through part that extends toward the well structure from the third through part to penetrate the gap-fill insulating layer, the channel layer, and the multi-layered memory layer under the third through part and exposes the well structure therethrough.

16. The method of claim 14, wherein the channel layer is separated into channel patterns in the exposing of the well structure, and

each of the channel patterns includes a first end part adjacent to the conductive pattern and a second end part adjacent to the well structure.

17. The method of claim 16, wherein the well contact line connects the second end part of the channel pattern and the well structure, and

the source contact line is connected to the first end part of the channel pattern.

18. The method of claim 14, further comprising, before the forming of the source contact line, forming an inter-well-source insulating layer by oxidizing an upper portion of the well contact line.

19. The method of claim 14, wherein the forming of the source contact line includes:

forming a silicon layer including the second conductivity type dopant;

changing a top end of the silicon layer into a metal silicide layer by using a silicidation process; and

forming a metal layer on the metal silicide layer.

20. The method of claim 19, wherein a source junction is formed inside the channel layer as the second conductivity type dopant in the silicon layer is diffused into the channel layer during the silicidation process.